Another PET 2001 8C that wants to live

[Tapon]

Hello everyone! First, let me introduce myself from Spain.

This is my first time posting on this forum, but I've been following you for a few years.
In fact, you've helped me repair an MZ-80A, and I've given several ideas for repair a Newbrain, and an Osborne... But above all, you've always been a great place to learn.
Now, a PET 2001 8C has come into my life. I've had it for a few weeks, and you've already helped me get it running. However, I've reached a dead end and don't know where to go from here.

That's why I'm contacting you, to see if we can revive another PET.

The latest symptoms (and its current state) are as follows:


- With A15 always HIGH, /SEL0 and /SEL1 are also always HIGH (I have checked the 74154 and it works correctly)

- In this situation, H8 and H9 are never enabled.

- And the outputs of I9 (74LS139) are always HIGH and don't enable the RAM chips because /CS in RAM chips is always HIGH.

- I tested three 6502 CPUs (Rockwell, Synertek, and UMC) and obtained the same results with all three. It's worth noting that the Rockwell produced some rather unsightly peaks on the rising and falling edges of the bus waveform (chinese copy???)… but the monitor displayed the same as the other two CPUs.

- It appears to read the EPROMs correctly, according to what is displayed on the screen.

- To test the system, I tried placing RAM chips in two different ways:
I8-J8, I7-J7
I8-J8, I4-J4
The same thing happens in both cases

- I've tried using RAM chips model uPD 2114 LC-3 (200ns) and TMM314AP (450ns), which appear to be working. When I connect them as video memory in C3 and C4, the screen displays the characters mentioned, and the 2114 RAM tester (although not very reliable) indicates they are good.

- The original RAM chips were MM2114N (450ns).

- The initial RESET and the installed RESET button time correctly for 1-2 seconds

- I have replaced the following ICs:

I1 to I9
J1 to J9
H1 to H9
G2 to G6
D2, D3, D4
C3, C4
B3, B4

I've created a small document that helps me track the repair, and I want to share it with you in case it might be useful to any of you. It shows the signals on the 6502 pins as well as at other points in the memory decoding system.

If I've missed anything or broken any rules unintentionally, please let me know.

Thank you all and greetings from Spain !!!

 

[daver2]

Welcome to VCFED (as this is your first post).

My advice is that you stop replacing parts needlessly...

1. What (exactly) is the assembly number on the PCB you have?
2. I see you are using my PETTESTER - so that is good!
3. Do you have the manual that came with my PETTESTER that tells you how to use it?

The test is 'stuck' at the video RAM test. In this mode I would expect to see lots of activity on SEL8 (access to the screen) and /SELE (access to the EDIT ROM) - and this is what we observe. So far so good.

4. Does the pattern on the screen conform to the pattern within my manual? The 'snow' is an artefact of asynchronous accesses to the video RAM on the PET 2001 series machines.

5. If the patterns match - the video RAM is being correctly written to (and displayed on the screen) but it is likely that video RAM reads are not working correctly.

6. Stuck at this test, my PETTESTER will not use any of the main RAM or any of the other ROMs (my PETTESTER is stand-alone and takes over the machine).

7. Have you FULLY tested the DC outputs from all of the four (4) on-board +5V regulators. You are looking for DC accuracy to as close to +5V as you can (certainly within +/- 0.1 Volts) and AC coupling noise/ripple of < 0.1 Volt. Does this mean anything to you?

8. I would concentrate on pins 1 and 19 of ICs B3, B4, G5 and G6 (244 data buffers). It is possible that we are missing a 'read' control signal or one (or more) of the 'read' buffers of the aforementioned 244 buffers could be faulty.

Dave

 

[daver2]

I am a bit confused about you using a 2532 EPROM in H4 for the Kernal ROM.

Assuming I have chosen the correct schematics, each ROM is a 2K device not a 4K device...

What do you observe on the PETs actual monitor?

Dave

 

[Tapon]

Thanks Dave for the quick response.

1. Logic Assy 320137

2. Yes, thanks!!!

3. Yes, I have the manual but I haven't read it completely.

7. I think the readings are correct. I've attached a "Volts" image.

8. I think the signals are correct except for pin 19 (H8-H9), which shows a constant HIGH value. From this, I understand that the data cannot be transferred to the data RAM. I've attached a "Buffers" image.

On the other hand, /SEL0 and /SEL1 are also HIGH, and I understand that I9 is blocked... Do you agree?

I'm also a bit confused about the EPROMs... As I understand it, it's possible to install the 2k EPROM group (image attached) or the 4k EPROM group (image attached), since they are selected in pairs (H1-H5, H2-H6, and H4-H7, leaving H3 as a single 2k pin), but I'm not convinced about either option.

Before I started replacing the ICs, I installed the 2k EPROMs and all I saw on the screen was garbage... I haven't tried them again since the replacements.
I'll try again tomorrow with the 2K EPROMs and let you know.

Carlos

 

[daver2]

Hi,

3. Well, read the manual!

7. The DC voltages look OK to me also. The limits are +/- 5% of 5V (for the TTL devices) = 5V +/- 0.25V = 4.75 to 5.25.

These are the limits specified by the manufacturer. These devices are old, and I don't like operating things at the limits - so I would say that 4.9V to 5.1V are what you are looking for. All of your voltage readings lie within tat range.

HOWEVER, this is not the FULL story. Ripple and Noise also contribute to the limits. Ripple occurs at either the main frequency (50/60 Hz) or twice the mains frequency (100/120 Hz) depending upon where you live. Ripple is a good indication of the state of the power supply rectifiers and smoothing capacitor(s). To measure the ripple, set the oscilloscope channel to AC coupling and the timebase to (say) 10 ms/div and measure the voltage rail. Increase the Y sensitivity of the channel until you observe some ripple. It will be present. Look at the positive and negative max and min voltages. Are you now outside of the limits of +/- 0.1 Volts?

Noise is related to (well) switching transient noise. You use the same measurement technique as for ripple, but you speed up the oscilloscope timebase to find a frequency at which the noise amplitude is a maximum. Again, is this transgressing the +/- 0.1 Volt limit?

8. If these r4eadings are being observed with my PETTESTER running, then you are misunderstanding what is happening. With the video RAM test failing (as in your case) the data RAM is not being accessed at all - hence no activity H8/H9 pin 19 and /SEL0 and /SEL1. As a result, I9 never selects any data RAM - so the PET is 'working' correctly at this point because NO data RAM is being selected. I would be more worried if data RAM was being selected!

Actually, using a 4K device in H4 appears to work! I hadn't noticed this before.

Please do not start swapping things around until we have run the testing that I proposed earlier. Exchanging parts causes IC socket wear.

My PETTESTER is telling us that it is unable to correctly read the data from the video RAM. We ned to explore this issue first without changing the machine.

I have a meeting now, but will read the rest of your post later...

EDIT:

8. Pins 1 and 19 of B3, B4, G5, and G6 look fine as control signals.

I will post the video RAM data line tests later after my meeting.

Dave

 

[daver2]

Meeting finished. Back to your PET problems...

The video RAM test works as follows:

1. Fill the entire video RAM with the values from $00 to $FF - repeating as necessary.
2. Read back the video RAM and ensure that the values read correspond to the expected values.

As a result, there should be a group of video RAM writes followed by a group of video RAM reads. This is repeated indefinitely (assuming the test is failing).

Filling the video RAM with the values of $00 to $FF means that D0 should be oscillating very quickly with each higher data line number oscillates at half of the frequency of the previous data line number. However, I need something to qualify this statement by - at what point (in time) are we monitoring the state of the data bus - because the data bus is used for ALL data transfers between (for example) the ROM and the CPU, and both the video RAM reads and writes?

The key bit of the video RAM circuitry (including the first set of data bus buffers - B3 and B4):



Schematic link: https://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/2001/320137.pdf.

When B3/B4 pin 1 goes LOW - this enables the "read buffer" half of the 244 buffers B3 and B4. The CPU is specifying the address of the video RAM location to read at this point in time (not the video circuitry).

At this time, the data bus signals from the video RAM (SD0-SD7) will be valid as should the data bus signals from the buffers B3 and B4 (BD0-BD7).

Set your oscilloscope up to trigger on a high to low transition on B3 or B4 pin 1. Use your other probe to look at BD0-BD7 in turn when the trigger signal (B3/B4 pin 1) is LOW.

BD0 should be observed to be LOW followed by HIGH on each successive B3 pin 1 LOW state.

BD1 should be observed to be LOW, LOW followed by HIGH, HIGH on each two successive B3 pin 1 LOWs.

BD2 should be observed to be LOW, LOW, LOW, LOW followed by HIGH, HIGH, HIGH, HIGH on each successive B3 pin 1 LOWs.

You will have to adjust the oscilloscope timebase to see the progressively longer sequence of HIGHs and LOWs.

Hopefully, you will find a BDn line that is stuck permanently HIGH or LOW when B3 pin 1 is LOW?

Don't worry if you don't though. If B3 and B4 are OK - we have to perform a similar test on G5 and G6 that buffers the BDn signals further before they reach the CPU data bus itself.

If all this makes sense?

Dave

 

[Tapon]

Back again.

To take these measurements (both the ripple and now the data bits), I had to borrow an oscilloscope... The keys on mine aren't working, and I can only see waveforms without being able to analyze them.
I've attached an image with the ripples from the four regulators... They seem to be correct.

Understood!!! Now I'm going to test B3-B4 and G5-G6... Let's see what I find.

PET TESTER manual read! Point 8, which you mentioned yesterday, is starting to make sense.

I'll let you know as soon as I have the results.

Carlos

 

[daver2]

Excellent.

I assume those measurements are really noise as opposed to ripple?

Don't forget to switch back to DC coupling after using AC coupling. Avoid the rookie mistake!

Dave

 

[Tapon]

I assume those measurements are really noise as opposed to ripple?

Yes, I think the same. I believe it's just noise and no ripple at all.
In fact, the first thing I replaced were the four capacitors next to the regulators.

Don't forget to switch back to DC coupling after using AC coupling. Avoid the rookie mistake!

It never hurts to remember that...

I've attached screenshots of the test on B3-B4.

Ch1: Pin 1 B3-B4
Ch2: BDx

What I see is that there's data on all 8 bits, although with some kind of interference...
I haven't been able to get a clean signal on the BDx pins. Wherever I measure the data bus, the signals look terrible.
It's just that there's activity on the bus... but I understand that it's not valid data.

I expected to see well-defined HIGH-LOW pulses, like the one on pin 1

The address, control buses, and clock... all the signals are clear and noise-free... except for the data bus.

It's practically the same on G5-G6.

The good thing, I think... is that no bit is stuck HIGH or LOW.

A few days ago, I also checked the data bus with the PIAs and VIAs removed... with the same result.

Something on the data bus is interfering or reflecting.

While testing the BDx pins of B3-B4, on some occasions the characters displayed on the screen, instead of showing the four bands of normal and inverted characters, appeared all inverted. This is the only anomaly I've observed.

Apart from that, Mr. PET doesn't want to wake up...

 

[daver2]

I will take a look tomorrow.

Forget seeing 'sensible' signals on the data bus. It may be in a 'tristate' condition, so nothing is driving it...

Also, by not looking at the data bus during a specific time 'window' you may not observe a stuck data bit on the video RAM read cycle - because the same physical piece of wire is being used to write data patterns into the video RAM on the write cycle and it is this you are observing...

Is your video RAM in IC sockets and (if so) do you have 8 off resistors available in the range 1k to 10k for an experiment?

Dave

 

[Tapon]

Is your video RAM in IC sockets and (if so) do you have 8 off resistors available in the range 1k to 10k for an experiment?

Yes, I have the video RAM in sockets and I have the resistors you mentioned.
I'm intrigued by the experiment...

Carlos

 

[daver2]

So that clearly doesn't look correct!

Let's concentrate on one signal at first.

Setup Channel #1 of your oscilloscope to monitor B3/B4 pin 19 - triggering on a HIGH to LOW edge. This is the video RAM /WRITE and write data buffers enable signal. So let's have a look at what 'good' should look like first...

You should observe some low-going pulses on channel #1.

Adjust the oscilloscope timebase so you observe approximately four (4) low-going pulses on the screen.

Use channel #2 to monitor signal BD0.

What do you observe on channel #2 when channel #1 is LOW?

Dave

 

[daver2]

You are still under moderation - so some of your posts are being delayed in me reading them.

Dave

 

[Tapon]

You are still under moderation - so some of your posts are being delayed in me reading them.

Don't worry, there's no rush... And if you can give me a day off, I'd appreciate it...


I've attached the B3 captures.

CH1: Pin 19
CH2: Pin 17 BD0 in first pic
CH2: Pin 17 BD3 in second pic

It's really difficult to get a decent capture due to the noise in the BDx signals.
On BD0, I managed to get a clean signal after playing around with the trigger.
I also tried BD3, and as you can see, the signal is far from clean; I couldn't get it to sync.

I don't know if this is the right time to try what you mentioned about the resistors.

 

[daver2]

You are getting there with your oscilloscope. This is the best tool for what we are trying to do, so it is worth persisting with it...

Just to confirm, you are triggering on channel #1 of the oscilloscope.

There is another configurable parameter I forgot to tell you about. Can you check a control with the name CHOP/ALT and make sure it is set to CHOP please.

The oscilloscope will draw the two channels separately. If we are trying to compare the traces in time, the oscilloscope has to chop between each channel quickly as they are drawn to preserve the time relationship.

Alt means that the oscilloscope first draws one channel and then the other - potentially losing the time relationship between the two - which is exactly what we need to preserve!

Dave

 

[Tapon]

I remember seeing the Alt/Chop control on the Hameg analog oscilloscopes I used for my studies many years ago.

And now that you mention it, I'd completely forgotten about that control...

In fact, I've checked it on both my own oscilloscope, which isn't very good, and the one I borrowed. Both are digital oscilloscopes, and no matter how much I've searched the manuals, I can't find that function.

Searching online, it seems that modern digital oscilloscopes, by processing input channels in parallel, don't need that function... or at least that's what I think.

 

[daver2]

Ah, so yours is a digital scope (it looked like an analogue one to me - hence the warning). Ignore what I said then - a digital oscilloscope doesn't have this feature.

In which case, I am not seeing in your first image of post #14 (on BD0) what I am expecting.

When pin 19 is LOW, it looks like BD0 is LOW also... This doesn't make sense to me (especially if the display is correct!).

I need a think...

Dave

 

[Tapon]

This doesn't make sense to me (especially if the display is correct!).

I'll use the weekend to repeat the BDx tests. Let's see if I can get signals with less noise.

On the other hand, I'll try tracing the signals through the different logic circuits to see if anything unusual appears... I'll keep you posted.

Also, I still need to check the monitor before connecting it to the motherboard.
I hope the monitor isn't too troublesome.

 

[Tapon]

Well, the weekend wasn't very productive in terms of troubleshooting. The only noteworthy thing was that after pressing the makeshift RESET button, the entire screen switched to inverted characters, as shown in the attached image.
At that point, no matter how many times I pressed RESET (you can tell when it's working because the noise disappears for those two seconds), the image remained inverted. After leaving it off for an hour, it returned to the familiar screen.

On the other hand, I checked the lines going to B2 (LOAD and CLK); they're receiving clean pulses, but the other outputs D0...D7 and Q and /Q are very noisy, similar to those I sent previously. I'm also attaching sheet 3 of the schematics, updated with the two blue jumper wires that these boards have on the bottom and the cut trace. I don't think it's related, but here's the updated schematic.

Another point that caught my attention was the Q and /Q outputs of C8.
They were very narrow pulses (1 ns at a frequency of 1 MHz, I think I remember). They were so short that they only reached a voltage of 2.7 volts. I've attached a hand-drawn image... I forgot to take a photo.

In summary, all the signals I tested were clean except for the data bus at any point on the board, including the A2 to B2 bus, which, being "isolated", I thought would show clean signals.

Carlos

 

[daver2]

B2 is the parallel to serial converter for the video signal. We already know that is working OK because we have a screen-full of correctly formed characters when you press your makeshift reset button.

If you have snow on the screen (as you do) what you are observing on the data and Q and /Q pins of B2 is an oscilloscope representation of the snow...

Press (and hold) the reset button - and the 'snow' should clear up on B2.

When C8 pin 3 (Q) goes TRUE, this sets one input on D8/10. When this is coincident with the 8 MHz clock on D8 /9 being HIGH, this resets C8 via pin 13. This is why you get a narrow pulse...

Since your video RAMs are in sockets, remove them completely. This should give you a checkerboard pattern on the screen (actually, it is an inverted checkerboard pattern - but let's ignore this).

You should now be able to look at B3 pin 1 (trigger) with your oscilloscope verses B3 pin 17. When pin 1 is LOW, pin 17 (BD0) should be HIGH. This should also be true for all of the eight (8) BDn signals,

Dave