stepleton
Veteran Member
I think Christian Corti's the one who must have distributed an annotated ROS disassembly.
If his disassembly is based on my ROS dumps, it might make sense to see whether the mystery instruction was actually OCR'd correctly from the IBM 5100 display. Here are the raw images I used... let's check. $5F1A/$200 = 47.something, so let's look at the 48th image in the album: yep, looks like it's correct. Too bad, no super easy answer
It's possible that the $02 argument to CTRL $1 does something mundane like putting the ROS controller into a known "reset" state. I spent a moment looking at the 5100 logics in the MIM, with a particular interest in the top of page 272. There are several things I don't understand about that diagram, but I think it's likely that the Sub Dev Address register holds the choice represented by CTRL $1, and that it's possible that any choice besides APL or BASIC gets represented as "no choice". That would mean that $02 would disable both "+APL Selected" and "+BASIC Selected", which also disables "+Dev Adr 1 Gated", and
(next page)
that means that the bus driver on the bottom right is disabled, so the executable ROS can't drive the bus.
AH, WAIT! I'm wrong. I just remembered that IBM numbers bits backwards. Go back to page 272, note that the SELector at top centre can only hear bits 6 ($02), 5 ($04) and 4 ($08). That means an address of $02 enables "+Dev Adr 1 Gated" with "+APL Selected" and "+BASIC Selected" disabled. (The other bits go into the selector gate, meaning addresses $0F and higher are ignored.)
What that's for I'm not sure about, but I bet the answer lies on page 273. I may come back to it later. I still like my hypothesis of this being a reset of some kind. Maybe it could allow you to set the address counter without actually causing the ROS storage cards to try and look up the address you're setting?
If his disassembly is based on my ROS dumps, it might make sense to see whether the mystery instruction was actually OCR'd correctly from the IBM 5100 display. Here are the raw images I used... let's check. $5F1A/$200 = 47.something, so let's look at the 48th image in the album: yep, looks like it's correct. Too bad, no super easy answer
It's possible that the $02 argument to CTRL $1 does something mundane like putting the ROS controller into a known "reset" state. I spent a moment looking at the 5100 logics in the MIM, with a particular interest in the top of page 272. There are several things I don't understand about that diagram, but I think it's likely that the Sub Dev Address register holds the choice represented by CTRL $1, and that it's possible that any choice besides APL or BASIC gets represented as "no choice". That would mean that $02 would disable both "+APL Selected" and "+BASIC Selected", which also disables "+Dev Adr 1 Gated", and
(next page)
that means that the bus driver on the bottom right is disabled, so the executable ROS can't drive the bus.
AH, WAIT! I'm wrong. I just remembered that IBM numbers bits backwards. Go back to page 272, note that the SELector at top centre can only hear bits 6 ($02), 5 ($04) and 4 ($08). That means an address of $02 enables "+Dev Adr 1 Gated" with "+APL Selected" and "+BASIC Selected" disabled. (The other bits go into the selector gate, meaning addresses $0F and higher are ignored.)
What that's for I'm not sure about, but I bet the answer lies on page 273. I may come back to it later. I still like my hypothesis of this being a reset of some kind. Maybe it could allow you to set the address counter without actually causing the ROS storage cards to try and look up the address you're setting?