T-Squared
Veteran Member
I had already confirmed that the inputs were good with the logic analyzer, connected to DATA-IN on all bank 0 chips (only 8/9 mem chips on the entire board, ignoring the extra parity chip that I added) during a few tests before.
As I was tracing out more of the diagram, I found that the way the memory is connected together, using DATA-IN and DATA-OUT, is weird. (I will draw up a diagram later)
I know the LPT Card needs to be taken out of the equation, but as a quick test so I wouldn't burn out myself trying to mess with the tangle of wires on the analyzer pod, I bent out the DATA-OUT pin from bit 1 (Chip 2 out of 8 in the bank):
640k mode:
LPT Analyzer card reported a value of 02, not 00, at addresses 0001 and 0005.
256k mode:
LPT card reported value of 57.
Actual value expected: 55.
(Addresses 0003 and 0007 not included, because they use the different "AA" value. Even so, they still read "FF". I'll try to burn the test chip with all the same test value tomorrow.)
Are there bit inversions happening that should not be?
As I was tracing out more of the diagram, I found that the way the memory is connected together, using DATA-IN and DATA-OUT, is weird. (I will draw up a diagram later)
I know the LPT Card needs to be taken out of the equation, but as a quick test so I wouldn't burn out myself trying to mess with the tangle of wires on the analyzer pod, I bent out the DATA-OUT pin from bit 1 (Chip 2 out of 8 in the bank):
640k mode:
LPT Analyzer card reported a value of 02, not 00, at addresses 0001 and 0005.
256k mode:
LPT card reported value of 57.
Actual value expected: 55.
(Addresses 0003 and 0007 not included, because they use the different "AA" value. Even so, they still read "FF". I'll try to burn the test chip with all the same test value tomorrow.)
Are there bit inversions happening that should not be?
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