6809/6821 to 8255/Z80 interface

Hi! Is there anyone with experience with interfacing 6821 to 8255 that can help me with an N8VEM project? I am building a 6809 host processor for the N8VEM system. The 6809 uses the 6821 to communicate directly with a 8255 which is a peripheral on the N8VEM SBC via the ECB backplane.

Basically the 6821 and 8255 form a parallel bridge. I'd like to use the automatic handshaking features of the 6821 and 8255 if possible. However, my prototyping has only had mixed success so far.

I could really use a hand for someone to look over this design and see what I am doing wrong, etc.

Thanks and have a nice day!

Andrew Lynch

Andrew, your 8255 programming looks okay, but I have learned to despise the 6821 PIA (Pain In (the) A**) chip. IMOHO, not one of Motorola's best efforts.

Have you considered using a MC146823 instead? It's probably a better match for the 8255.

Chuck(G) said:

Andrew, your 8255 programming looks okay, but I have learned to despise the 6821 PIA (Pain In (the) A**) chip. IMOHO, not one of Motorola's best efforts.

Have you considered using a MC146823 instead? It's probably a better match for the 8255.

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Hi Chuck! Thanks! Well, you have a good point there with the 6821. Not only are they hard to program they are difficult to get as well.

One thing that is further complicating this design is that the 6809 relies exclusively on the PIA for its IO which really makes debugging a PITA. The 6809 is not a true SBC in that it is not controlling the ECB and doesn't have its own serial port. To keep the design very simple (low chip count, low cost) the 6809 host processor is basically just a CPU, ROM, RAM, PIA and minimal glue logic.

My plan is to use the PIA to interface to the 8255 and then the N8VEM SBC accesses the 8255 as a peripheral over the ECB. The N8VEM SBC would serve all the IO the 6809 requests through the 8255/PIA interface. At this point I am not all that fussy about which PIA chip the 6809 uses to talk to the 8255.

I am set on using the 8255 on the ECB side though since interfacing it is very easy and I rather like that chip. Yes, it has its problems but at least I am somewhat familiar with them. It also only needs one 74LS32 to interface to the ECB prototyping board with unique addressing and that's nice.

In particular the 6821 port B seems to be misbehaving the most. I noticed that the A and B sides have different electrical loading characteristics and wonder if the 8255 TTL inputs/outputs are somehow confusing the 6821. Obviously I need to experiment with this more to figure out what is happening but I need to finish Hargle's XT-IDE prototype board first, then work on this.

Thanks and have a nice day!

Andrew Lynch

If you're having trouble finding 6821s, there were/are a number of different versions; 68A21,-B21,-C21 and 6521 to name a few; even the older 6820s & 6520s *might* work for ya but ISTR there was an issue with needed pullups.
Lots of 6502 systems used 'em as well, not only 6800/09 systems.

You might consider just using a couple of 8 bit latches on the 6809 side (LS374) and let the 6809 manage the handshaking details. That is, when the Z80 writes to the 8255, generate a 6809 interrupt and let the 6809 generate the ACK. The real estate would probably be about the same.

Another alternative would be to dispense with the 2-chip solution and use something like the DS1609 dual-port RAM. If you wanted to stay "period", you could use an MC68HC34, which is a more 6800-ish part.

The 6522 is bus compatible with the 6809, but obviously the pinout is slightly different. It does have some useful timers though.

lynchaj said:

Hi Chuck! Thanks! Well, you have a good point there with the 6821. Not only are they hard to program they are difficult to get as well.

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Jameco carries them. I've bought probably 500 from them over the last 5 years.


Vince

Hi! The good news is I found the problem with the N8VEM 6809/6821 host processor. The 6821/8255 interface works fine but my 6809 test software contained a "meatspace error". I had mixed up the 68xx/65xx direct versus immediate addressing modes resulting in random SRAM data being used to initialize the 6821. Z80 has no direct addressing mode and I had completely forgotten about it on 68xx. It has a big effect on 6821 initialization... :-/

Once I found the problem and made the corrections, the interface works fine. I had to put in some pull up resistors on the 6821 port B since it did not seem to be able to rise to HIGH levels but I'll try removing them and see if it still works without them. The no handshaking interface works great as-is and even the handshaking mode mostly works.

The good news is spending all this time reviewing the design has given me some more ideas. I noticed that if I use a DS1220 rather than a 28C16 EEPROM or 2716 EPROM, that the battery backed SRAM effectively gives the builder another 2K of SRAM to work with. It is not completely free since the 6809 has to boot from something (reset vectors & boot code). Almost the entire 64K memory map is RAM with the exception of the 2K addresses needed for IO.

I am considering adding a RAM memory page configuration latch similar to the N8VEM SBC design to allow use of 512Kx8 SRAM parts. It'd be simple to allow swapping of the lower 32K RAM page and give the builder a lot more RAM. From what I recall of previous 68xx designs I've used they have seemed lack sufficient RAM. Sharing IO with RAM/ROM memory just makes the situation worse. However, its been quite a while and my memory is fuzzy.

Thanks and have a nice day!

Andrew Lynch