At a low level, the following is what I am positive is happening.
Refer to the POST breakdown [
here], which is for the BIOS revision that the OP has.
First, step 2 is relevant. The action means that if a RAM parity error is encountered during the POST, that the resulting NMI will not cause a jump to the NMI handler, which would display "PARITY CHECK" and then halt the CPU.
First 16 KB
At step 13, a test of the first 16 KB of bank 0 is done. The test involves a single call to a particular subroutine, one that tests a specified 16 KB block. The subroutine tests the data bits and the parity bit. Failure of the parity bit is indicated if data read equals data written, but a parity error occurs.
Example: Byte written = 55h, Byte read back = 55h, Parity error = yes
The POST looks for a parity error by examination of the PC7 pin on the 8255 chip (diagram [
here]).
On the OP's motherboard, this test is passing (because if it wasn't, the CPU would get halted [without any error indication]).
The passing of this test also indicates that there is not a fault in the parity generation/read circuitry such that false parity errors are always being generated.
Remainder of RAM
Done at step 23. The same subroutine referred to earlier is used. The subroutine returns a fail status if either the test byte written does not match what was read back, or if a parity error occurred. Also returned is a byte representing the bit difference between what was written and read.
In this test is where the OP's "0400 201" is being generated.
The "04" indicates the fourth 4 KB address block (i.e. failing address somewhere between 16 KB and 20 KB).
The "00" is the bit difference between the byte written and what was read back, and because it is zero, the data bits are good. Therefore, it was a parity error alone that resulted in the subroutine returning a fail status.
We know from the successful test of the first 16 KB that the parity circuitry is not always generating false parity errors. Therefore, a failure of the parity bit is indicated.
After "0400 201" is displayed, the POST continues.
PARITY CHECK 1
At step 36, NMIs are allowed though to the CPU. Consequently, any future read of an address that produces a parity error (whether that's due to a data bit or parity bit) will invoke the NMI handler, resulting in a display of PARITY CHECK 1 for motherboard RAM, or PARITY CHECK 2 for RAM on expansion cards.
