Recent content by dreNorteR

Yes, the description of the erratum says that happens. But you could never reproduce it, and I suspect it may be the result of someone at Intel being misinformed about what the exact issue is, and confusing it with another one, mainly because it gives absolutely no reason why CX should be...

When a repeated string instruction causes a fault, that can leave CX and SI/DI inconsistent because they aren't restored correctly to the values they had before the fault (similar to SP in the case I mentioned above). Did you mean that, or some other erratum? edit: yes I've read now what you...

The shutdown from stack wrapping around may not always work correctly when in real mode. I remember setting SP to 0001 and doing either a push or int3, expecting it to shutdown+reset, but got an int 08h or 0Dh instead. Seemed like the first push was aborted, but it then failed to "roll back" SP...

The shorter opcodes are only for AL/AX with an immediate operand. Intel wanted to make typical 8080 code translate to be roughly the same size, but anything with two register or reg/mem operands has to use the ModR/M byte since there simply aren't enough single byte opcodes left. If there was...

Does this only happen at FFFF, or whenever IP points to the last byte in the segment limit, and it's an odd address?

They are probably not connected except on the chips that were produced for the In-Circuit Emulator, or maybe some early samples. They are used for testing, and are in the same location as the "NC" pins, but have no bond wires. See this die shot (pin names added by me, original and larger version...

There are three stages in the pipeline: 1. The prefetcher does bus cycles to read up to 6 bytes (three 16-bit words). This should only happen at a low priority when the CPU has no other bus access to do, and isn't about to execute a jump, but as we've seen this doesn't quite work correctly. 2...

The patent mentions several times that prefetch would be suspended as soon as a jump instruction is decoded. Strange that this doesn't seem to work at all.

I barely know anything about this electrical stuff, but as MiaM said, the Arduino may be keeping some parts of the chip powered. The third run is probably the cleaner one! From my experiments I seem to remember that while the values of those registers not clobbered by the BIOS during POST looked...

That makes sense. I noticed that the bus state after STOREALL is shown as PASV[F] instead of PASV[7], which is another indicator that it's actually expecting to fetch code! It's very unlikely that a random 286 chip has these pins exposed, only those produced for In-Circuit Emulators. Maybe...

Not sure why the registers are still set like that, you basically powered up the CPU, released it out of reset and the first two words of code it fetched were 0FF1, xx04? Or was there anything else in between? Thanks for including enough cycles after it stops writing to memory, this is very...

That should be possible with just LOADALL, Digital Research did this as well but apparently their method didn't work on all steppings - could you explain more about what you used STOREALL for? So far, the one intended use for this instruction I've seen was to generate an ICEBP via software...

Very interesting to me, since I only played around with what could be done using software running on a normal AT compatible! Was thinking for a time about building an interface like yours, but it's not really something I have experience with. Seems like there is something going on internally...

Apple made the deliberate choice of 'decomposing' Unicode characters wherever possible. So åäöÅÄÖ becomes aaoAAO + combining diacritic marks. No other operating system does this.

Coming up with a single 'correct' mapping for all purposes seems like an impossible task to me. You won't reproduce the glyphs exactly when using another font, and I believe the ones from https://int10h.org/oldschool-pc-fonts currently don't support your mapping (though maybe they will in the...