Recent content by jonny64

Hopefully last slightly off-topic: My PAL research work which evolved out of this thread is now finalized and published at https://github.com/jonnyh64/palrvs.

If there is really a chance that your power supply is making trouble, I‘m willing to sponsor one of these neat picoatx supplies - just let me know.

Erm, is there more than U87 and U130?

@Chuck(G) , thanks for the clarification. In the meanwhile, I found https://nsa40.casimages.com/img/2021/03/25/210325010228265393.png, which dates back to 2007. I‘ll take this as earliest reference for the idea and will not dig any further.

Rodney, congratulations for reaching the "published on GitHub" milestone. What an awesome project!

As I plan to set up a GitHub page with information about PAL16L8 reversing together with my Python scripts, I want to make sure to credit everybody appropriately, as the core ideas are surely not my merit. @Chuck(G), are your forum posts from Oct 2011 the first appearance of the brute force...

Rodney, thanks for testing my jed files!! The "EPROM dump" was binary different, and I found the reason: The DIR_245 equation generated by pete.py was wrong. pete.py: !DIR_245 = AEN_2 & AIOW & !XBHE # MEMW & RAS & !AEN_1 # AEN_2 & !MEMW & !XBHE; Equation found by you: !DIR_245 =...

Rodney, did you check at aisler.net? Not sure how much more expensive they are, but maybe less surprises and no import tax…

As I hate hand wiring such stuff. If somebody wants the KiCad files, just let me know...

I'm finishing my PAL reversing work which evolved out of this thread and would like to summarize a little... With the help of Eudimorphodon (thanks!!) and after studying PAL and GAL datasheets, I was able to write my own simplified GAL assembler which can convert the pete.py generated equations...

Rodney, thanks again for your patience. I think I slowly start to understand. :) PS: 1:1 after 67 minutes. I predict end result 2:1 :) :)

Rodney, many thanks for explaining all the ISA bus details - quite a while until I found enough time to thoroughly read through it. I was really concerned that this RAM connection choice reduces RAM performance, but it really doesn‘t seem warranted. Is SAx/SDx then directly connected to Ax/Dx...

Ok, after reading Eudimorphodon‘s post again, I understood that the clock on the ISA bus could be switched between full CPU speed and, e.g., 8 MHz. Sounds scary to me, but I‘m more or less a novice for such stuff. I still would think that a proprietary RAM expansion connector would simplify the...

Hi Rodney, I read through the last couple of posts, but I'm still a little puzzled. Looking at the 80286 pinout, it seems to me it has a very "classic" design: address bus, data bus, a few control lines and exactly one clock (named CLK). Connecting SRAM to it somehow seems obvious with...

And here are the equations I get for this IDE/floppy controller: !FDC_LDORn = SA1 & SA4 & SA5 & SA6 & SA7 & SA8 & SA9 & !AEN & !SA0 & !SA2 & !SA3 !FDC_LDORn.OE = 0 !FDC_LDCRn = SA0 & SA1 & SA2 & SA4 & SA5 & SA6 & SA7 & SA8 & SA9 & !AEN & !SA3 !FDC_LDCRn.OE = 0 !IDE_CS1n = SA1 & SA2 & SA4 & SA5...