The lower and upper 64k are the same chips. The memory array is 64kx16. IMHO having this many DRAM-chips going bad is not very likely.
You could test the theory by removing one of the chip that always reads 0 and re-run the test.
Could there be a bad buffer? I am mostly thinking that bad...
Yes. They are fixed frequency.
Back inte the day I spent quite some time configuring XFree86 modelines for various fixed frequency monitors.
Of course it didn’t sync when it did the power on test. But the monitors were almost free so it was worth it…
I don’t remember that there were driver...
I think you had the wrong input signal. Either wrong polarity or frequency. Or the screen required sync on green.
If the screen showed some kind of picture they are likely to be fine although I have one like these that has a capacitor problem in the video section. The picture is stable but the...
I am not sure what you want to do. But if you want to have another branch it as simple as do a git checkout -b <new branch>. Then put your files there and commit changes and push the new branch. You need to do a git push --set-upstream origin <new branch>. In the Github GUI you can then select...
Are you certain that the ROM address counter is reset when reading the ROM Data register? I.e have you written to the ROM address register in order to reset the counter?
I don't think the HDD nor the floppy controller had a Diag ROM as the DECNA has. They only have one single word that is the...
Most likely not unibus. Just hex size,and for some reason they kept the contact fingers. The fingers aren’t even gold-plated. Maybe for testing purposes?
Thanks! I wonder how the BRPLYL signal is generated on the CTI bus. Surely a ACK / READY signal from the 8207 has to be involved somehow. A CTI RAM access may be stalled since the 82586 is accessing the RAM and then the CTI bus transaction has to wait. Is the signal AACKAL used somehow to...
Thanks for checking this. Obviously I mixed things up.
It says in the tech manual that XACKA L goes to the CTI memory Data latch so it is indeed exactly what you have written. What I wanted you to check was to check where the AACKBL (5) signal goes. It should go through a 7404 and then to...
No the ROM is not behind the 8207. The 8207 only handles DRAMs. I.e. it has row/column multiplexing logic and refresh management. There is a simple counter that addresses the ROM and each time you read from baseport+0 you get the current data from the ROM and the counter is incremented. Then if...
You should be able to rip out parts of the diagnostic that sets up mapping. I think the PAR is restored back using EMT 6 after the test is concluded. But if you just call EMT 5 with proper parameter you should have you mapping set up. Somewhere you need to write to the base register in the DECNA...
It is indeed real memory. But it is also a dual-ported shared memory. The 82586 ethernet controller has all its buffers and control structure in this space.