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Hi Johann, My congratulations on your published status for your very cool project! I read your readme doc on Github, very informative and complete! I look forward to trying out your solution with the next suitable PAL chip I encounter. Thanks for your help and for the pleasant conversation...

I have some great news about the project! I spent a little longer working and testing on the prototype mainboard before starting the modifcations on the 5170. I will probably start this work tomorrow. I have now solved the power on problem, and the prototype is starting and running stable at...

I have done a lot more testing and reviewing of schematics. The biggest change I am seeing in the 5162 is how they controlled the conversion logic. The timing is more nuanced and by making it more accurate and elaborate, this can provide the zero wait state resulting situation that HoJoPo...

Hi HoJoPo, I see, interesting! will check the schematics, possibly I can test with this change as well with some updates.

Hi modem7, Thanks for your message and pointing out this fact. That's very interesting, I didn't realize that before. I will spend more time to check the 5162 schematics.

Hi Johann, I'm sorry, I completely didn't see your post of april 23rd. Just now I was reading back my findings and came across your post. Thanks for the offer to sponsor a pico power supply. I don't believe the PSU is an issue, I also tested with some big harddisks connected to the 12V rails...

I'm working in quartus at the moment. What I am trying to do is to find the translated logic for certain parts of the system control circuits post compilation. After finding a certain element I am trying to apply an appropriate delay to the output signal of that element which corresponds to the...

One of the things in the CPLD development which to me remained an uncertainty was the fact whether the interpretation of the "TRI" elements in quartus would be correct to reflect an actual pin going tri-state floating, or in case of a bidirectional pin, whether the pin would be able to return to...

I know a little more about how it works in quartus, apparently quartus analyses the circuit and makes a list of clock sources. These can be found in the timing program "Timequest timing analyzer" in the quartus tasks tree. After starting this program from within quartus with the project opened...

In the past when I was designing pure TTL systems it was easier to influence the timing. Or at least, I had a direct means to change the timing. What I did with those systems was to exchange the logic family of ICs in the decoders. By changing them to faster types, I could shorten the...

I have tested a lot of different combinations of transceivers, this resulted in a reasonably optimal setup as far as the transceivers can influence the system. Next I had a good look at various options in quartus. From my testing work I am starting to see the problem is related to timing in the...

I went back to the initial programming of the CPLDs and restored the ICs used in the initial testing. After doing this I was able to get the system to POST again. I started a debugging log where I am logging every change and then do some power cycle tests to record how many cycles are needed...

I have done a lot of testing, and expanded my list of things to look at. Last night I was even unable to get the CPU to run properly anymore. I am retracing my steps and restoring the initial situation. I can't exclude that there may be some marginal problem in one of the CPLDs even since they...

I have made a new XT-IDE AT configuration and tested with the primary and secondary IDE ports. It appears to work properly now. I can see a harddisk attached to the secondary, and I can see partition information in FDISK. I tested with a NTFS drive but I will format one later on. It seems that...

Indeed, I will test other BIOS versions yet. I will add it to my list. However the MR BIOS is the one BIOS in which I have the most faith. There are of course others, thanks Alvaro for the URL I will check it out. Today I tested with power-on reset enabled in the CPLDs and with disabling race...

A few more things resulting from my work so far. Possibly the DMA clock frequency was no issue and probably when the power cycle problem is resolved I will return the DMA controllers to the previous 4,77 Mhz operation or even the specified 5Mhz for performance reasons. If I can get DMA to work...

Hi Alvaro, It is great to hear from you! And thanks for your compliments, I appreciate that. Getting to this first prototype is a very important milestone for me to recreate the amazing AT design. I have a lot of appreciation and respect for the IBM AT designs and concept by Don Estridge...

Apparently the problem of needing many power cycles is not gone yet. There was some fluke which caused a few sooner stable cycles but later the problem returned and was the same. Also when test exchanging the load capacitors on the 82284 clock generator which occasionally caused the clock to...

I have done more testing and I have found one of the factors in the problem where I need many power cycles to get the CPU to stay active. I now have a correct power cycle happening after powering off and on about two or three times which is a huge improvement, previously I needed more than 20...

Hi rask, Yes, it would require desoldering the PAL chip from the board. Desoldering anything from a PCB, and even working with it and handling it, connecting, disconnecting etc. all carries risks. This is always the own and sole responsibility of any person who uses the information in this...