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Attached is the cleaned up and annotated DECNA memory test code. It has both a simple 8KB memory test and a full 128KB memory test very close to the ROM diagnostic implementation. Given the memory layout, the 8KB test should reveal most chip-level faults. After fixing a bug, disabling...

Sorry for the delay and let me start by saying thank you. It is because of FILLV that I was able to repair by EBO board. My temporary absence on this thread was because I recently acquired a DECnet card and found it had hardware problems on boot. I started a new VCF thread...

Pin 17 is pulled up to VCC.

I was going to change all memory, but every rework operation poses some risk to the board. So, I decided to just change out what was necessary at this point. If others go bad, I can replace and socket. Now that the card is functional, I need to return to setting up a network with a PC running...

Success! After considering some possible options, I decided that it was unlikely the LS logic had gone bad even though there were potentially 8 bad memory chips. Those transceiver and D latches are practically indestructible in my experience. I instead decided to trace the board to identify...

Thanks. I pulled the board and realized exactly what you said. In fixing and running the ROM code over my simple memory test, I found there are some locations where one of the bits toggles to the correct value. I located the 244 buffers and 373 D latches. Like you said, it could be an input...

Here's an update on my DECNA card debug. My program to test DECNA card memory led me on an educational journey to learn things that some of you probably know. After fixing the length calculation in the QIOW$S call, I proceeded to debug the memory test portion. It seemed to run, but I needed a...

I stuck a memory card in the cage to test MattisLind's suggestion. The memory card is octal 34. The result came back as 344. So, it is definitely a bug. I'll bet it has something to do with the QIOW string. Bingo! I replaced the length calculation in the QIOW$S call with the returned...

Yes, I clear the ROM address register just before reading the card ID. Attached is the code. The memory test is commented out and just the card enumeration runs.

I have an unexpected result and I am not sure what to make of it. I patched together a program to enumerate the CTI cards, read the card ID, find the DECNA card and then perform the exact memory test from the diagnostic ROM. The card enumeration and ID code is based on davibear's code. As a...

I found XACKAL connects to the input enable on two 373 latches and pin 13 on a 74LS00 (input to a NAND gate) on the other side of the board - likely part of the bus reply generator in the figure above.

Confirmed. AACKBL (5) signal goes to pin 13 on the 7404. Pin 12 output goes to READY (39) on the 82586.

Pin 37 ARDY/SRDY is on the right of the 82586 in the middle of the chip just above VCC (Pin 36). Pin 37 is an input and it has a hard ground. I confirmed Pin 36 is VCC. ~XACKA is pin 2 on the 8207. It connects to pin 11 (enable input) on a 74LS373 in the same column (E50) as the 8207, third...

Yes, I am of the same opinion about replicating the card. I think we have enough information and knowledge with this team to make it feasible. It took me a long time to find a card, and of course, the only I received did not work. I'll check into ~XACKA trace routing this evening.

Both of you are spot on. I was loupe'ing the board last night to look for open solder joints and other physical failures. As a general note, the soldering quality on these boards with the silver traces doesn't seem to be as good as the boards with the green coating. There are pits and gaps...

I worked my way through the code and it seems to be doing exactly what davibear said for Test 2, writing 0xAAAA, checking the pattern and doing the same with 0x5555 (I did not fully verify). Code 10 looks like a memory problem. I can replace all DRAM chips, but I was wondering if I could write...

So I ordered a batch of chips. Any guidance on how best to remove them from the board. I was thinking about hot air with a heat gun. I think you also suggested just cutting the chip leads and removing one at a time.

I bought one of the four available. I only have the one DECNA card, and it fails. I believe there were two other buyers, one who may have purchased two cards.

Thank you! This is very helpful. I need to study in detail later today, but at first glance it appears you and I have same variation board ("C1"), which means it has the same alternate part numbers for the memory chips. Manufacturing date seems to be close also. I did spot the wirework loop...

Thank you. This is a wealth of information! I did notice that there seemed to be two blocks of code, but I didn't know what to make of it. You explained it. I was looking at the code you identify as Test 2, which MattisLind pointed out as the subroutine at 3776, last night. It looks like...