Hopefully last slightly off-topic: My PAL research work which evolved out of this thread is now finalized and published at https://github.com/jonnyh64/palrvs.
@Chuck(G) , thanks for the clarification. In the meanwhile, I found https://nsa40.casimages.com/img/2021/03/25/210325010228265393.png, which dates back to 2007. I‘ll take this as earliest reference for the idea and will not dig any further.
As I plan to set up a GitHub page with information about PAL16L8 reversing together with my Python scripts, I want to make sure to credit everybody appropriately, as the core ideas are surely not my merit.
@Chuck(G), are your forum posts from Oct 2011 the first appearance of the brute force...
Rodney, thanks for testing my jed files!!
The "EPROM dump" was binary different, and I found the reason: The DIR_245 equation generated by pete.py was wrong.
pete.py:
!DIR_245 =
AEN_2 & AIOW & !XBHE
# MEMW & RAS & !AEN_1
# AEN_2 & !MEMW & !XBHE;
Equation found by you:
!DIR_245 =...
I'm finishing my PAL reversing work which evolved out of this thread and would like to summarize a little...
With the help of Eudimorphodon (thanks!!) and after studying PAL and GAL datasheets, I was able to write my own simplified GAL assembler which can convert the pete.py generated equations...
Rodney, many thanks for explaining all the ISA bus details - quite a while until I found enough time to thoroughly read through it.
I was really concerned that this RAM connection choice reduces RAM performance, but it really doesn‘t seem warranted.
Is SAx/SDx then directly connected to Ax/Dx...
Ok, after reading Eudimorphodon‘s post again, I understood that the clock on the ISA bus could be switched between full CPU speed and, e.g., 8 MHz. Sounds scary to me, but I‘m more or less a novice for such stuff. I still would think that a proprietary RAM expansion connector would simplify the...
Hi Rodney,
I read through the last couple of posts, but I'm still a little puzzled.
Looking at the 80286 pinout, it seems to me it has a very "classic" design: address bus, data bus, a few control lines and exactly one clock (named CLK). Connecting SRAM to it somehow seems obvious with...
So, here comes the explanation why we were not yet able to get the simplified U87 equations without some manual "tuning"...
First of all, from checking the whole "EPROM dump" and comparing input to output bits in a rather brute-force way, we know that the following 10 pins can impact the...
Good news: pa.py now outputs the same equations as PA.EXE, including "XBHE = AEN_2 & !XA0" instead of "XBHE = !AEN_1 & AEN_2 & !XA0". I've written a detailed explanation into the source code and won't repeat it here. Moreover, pete.py now outputs the same equations as PA.EXE + logic Friday...
Sorry, I didn't have much time this weekend, so only a small update...
One of the questions was, why PA.EXE and pa.py disagree about XBHE.
PA.EXE says:
pa.py says:
PA.EXE and pa.py agree on OE:
Without source code, I cannot say how PA.EXE infers that, but I know how pa.py works:
- First...