What I have not really understand is why is it a bigger problem for write than for read ?
Because the operation which give problem under CPM is clearly read. May be write dont work but this do not hang CPM.
May be its because the flip flop could be reset by R/W bus signal ?
May be I will start to think to an improved design of the FPU board with in and out latches to avoid timing problems.
But then I will have to read the status byte of the FPU to know if operations are terminated or not...