RobS
Experienced Member
Here’s a little problem for anyone who believes that they understand the architecture of magnetic core memories. I have encountered it while rebuilding the memory unit for a Honeywell 200, part of the project mentioned in this other thread Honeywell-200-resurrection I am basing the rebuild on the information given in Honeywell’s model 201 CPU manual which, for those wanting to check my facts, is available as a 9.7MByte PDF on Bitsavers here ETM200_201CP_Logic_Aug65.pdf
The Honeywell 200 uses a number of nine bit-plane four wire core memory modules with X, Y, sense and inhibit wires. The basic principle is easy enough to understand, that the total current in the X and Y wires is sufficient where they cross to flip one core in each plane, thus setting all the bits for one address to one. Each inhibit wire passes through all the cores in one plane and carries an opposing current which stops a core being flipped when that particular bit has to remain at zero. The inhibit current is only strong enough to reduce the effect of the X and Y currents sufficiently but not enough to flip any other cores in the plane back to zero by itself. That much I get, but the next part of the Honeywell memory architecture confuses me.
On pages 5-10 and 5-32 of the manual Honeywell explain that the inhibit wire on each plane is split in two with currents running in opposite directions in each half. To use their exact words “The reason for doing this is to reduce the noise coupled into the sense line and current coupled into the Read/Write lines.” To add to the confusion they also connect the corresponding half inhibit wires in adjacent pairs of memory modules in series, but this may be done just to present a full load to each of the driver circuits. Now I can see that the memory can be arranged in such a way that noise in the sense line is reduced as the sense amplifiers are symmetrical and treat a pulse of either polarity in the same way, so half the cores can be threaded by the sense wire the opposite way around to the other half, but I don’t see how they can claim that the current coupled into the read/write lines, i.e. the X and Y wires, is reduced. Surely the inhibit current must oppose the write current through every core and therefore have a cumulative induced effect, otherwise it wouldn’t do its job.
Perhaps there is a good reason for this architecture and Honeywell just gave a bad explanation, but it leaves me mystified. We do have a memory module which has been disassembled and could visually trace the actual path of the wires through the cores, but can anyone suggest how Honeywell’s claim could be wholly true?
The Honeywell 200 uses a number of nine bit-plane four wire core memory modules with X, Y, sense and inhibit wires. The basic principle is easy enough to understand, that the total current in the X and Y wires is sufficient where they cross to flip one core in each plane, thus setting all the bits for one address to one. Each inhibit wire passes through all the cores in one plane and carries an opposing current which stops a core being flipped when that particular bit has to remain at zero. The inhibit current is only strong enough to reduce the effect of the X and Y currents sufficiently but not enough to flip any other cores in the plane back to zero by itself. That much I get, but the next part of the Honeywell memory architecture confuses me.
On pages 5-10 and 5-32 of the manual Honeywell explain that the inhibit wire on each plane is split in two with currents running in opposite directions in each half. To use their exact words “The reason for doing this is to reduce the noise coupled into the sense line and current coupled into the Read/Write lines.” To add to the confusion they also connect the corresponding half inhibit wires in adjacent pairs of memory modules in series, but this may be done just to present a full load to each of the driver circuits. Now I can see that the memory can be arranged in such a way that noise in the sense line is reduced as the sense amplifiers are symmetrical and treat a pulse of either polarity in the same way, so half the cores can be threaded by the sense wire the opposite way around to the other half, but I don’t see how they can claim that the current coupled into the read/write lines, i.e. the X and Y wires, is reduced. Surely the inhibit current must oppose the write current through every core and therefore have a cumulative induced effect, otherwise it wouldn’t do its job.
Perhaps there is a good reason for this architecture and Honeywell just gave a bad explanation, but it leaves me mystified. We do have a memory module which has been disassembled and could visually trace the actual path of the wires through the cores, but can anyone suggest how Honeywell’s claim could be wholly true?