This really isn't an issue of fairness .. physical memory is well defined. I've not changed any rules or definition - no architecture text or OS would consider bank switched memory to be physical memory.
The 808x has 16 bit pointers. Segments are 64 bits. Using segment pointers and offsets the CPU can put any combination of 20 bits on the address bus. Looking at the 808x and claiming that it is bank switched because it uses a segment pointer and offset to generate the 20 bits for address bus seems a bit tortured to me, when the generally accepted definition of bank switching is using external hardware to bring the different banks of memory into view at a window in the memory map.
The same goes for the Z80 variants. The Z180 that you refer to has 20 address lines, hence the addressability of up to 1MB. (The DIP variant only has 19 lines, and only gets to 512K. This must be the version you referred to.) Zilog calls the extra hardware they put on the chip a memory management unit.
I think the key difference between an external bank switching mechanism and an 'on chip' one like on the 8088 and 8086 is that the external schemes are usually manipulated using memory mapped I/O or through I/O space, while a memory management unit is programmed using directly accessible hardware registers in the CPU. The 808x and Z80180 clearly have MMUs that generate their 20 bit addresses, not a hacked on bank switch mechanism like on a LIMS board.
If you choose to call an onboard MMU that is implemented with hardware registers a bank switching scheme, well, it is not. If it happens internal to the CPU and doesn't require extra hardware or setup to external latches on the bus, then it's physical memory. If you've got to program some I/O port to make it work, then it's a bank switching scheme.
It is very relevant. It's programmed different, it behaves differently. It's the difference between doing some I/O writes to bring a piece of RAM into view before putting a 16 bit address on a bus, vs. having the chip do it internally and generating a straight 20 bit address. The code to do it is different, and much faster when it is done by an integrated MMU.
The 808x has 16 bit pointers. Segments are 64 bits. Using segment pointers and offsets the CPU can put any combination of 20 bits on the address bus. Looking at the 808x and claiming that it is bank switched because it uses a segment pointer and offset to generate the 20 bits for address bus seems a bit tortured to me, when the generally accepted definition of bank switching is using external hardware to bring the different banks of memory into view at a window in the memory map.
The same goes for the Z80 variants. The Z180 that you refer to has 20 address lines, hence the addressability of up to 1MB. (The DIP variant only has 19 lines, and only gets to 512K. This must be the version you referred to.) Zilog calls the extra hardware they put on the chip a memory management unit.
I think the key difference between an external bank switching mechanism and an 'on chip' one like on the 8088 and 8086 is that the external schemes are usually manipulated using memory mapped I/O or through I/O space, while a memory management unit is programmed using directly accessible hardware registers in the CPU. The 808x and Z80180 clearly have MMUs that generate their 20 bit addresses, not a hacked on bank switch mechanism like on a LIMS board.
If you choose to call an onboard MMU that is implemented with hardware registers a bank switching scheme, well, it is not. If it happens internal to the CPU and doesn't require extra hardware or setup to external latches on the bus, then it's physical memory. If you've got to program some I/O port to make it work, then it's a bank switching scheme.
And it's really irrelevant if said hardware exists on-chip or off.
It is very relevant. It's programmed different, it behaves differently. It's the difference between doing some I/O writes to bring a piece of RAM into view before putting a 16 bit address on a bus, vs. having the chip do it internally and generating a straight 20 bit address. The code to do it is different, and much faster when it is done by an integrated MMU.