new PDP QBUS panel project

[Steve Toner]

You cant get there with a 16 bit counter. You would need to prescale the clock to the timer. The lowest clock divisor is 8.
3579545 divided by 8= 447443.125 not a good starting place to get to either 50 or 60 hz.
You could use a lower divisor and do additional division in the interrupt service routine or change the divisor each timer overflow to get a non integer divide.
But it starts to feel like a hack.

If you choose a common baud rate crystal like 3.6864 mhz. as the starting point the numbers work for both 50 or 60hz.
If i had intended to support both 50 and 60 hz this is ware I would start.

I never thought about supporting 50hz. as you questioned "Is it actually necessary".

OK, got it. So a limitation of the microcontroller. You'd need to divide by 13 to get to an integer that would fit in 16 bits, and Timer/Counter1 cannot be clocked from Timer/Counter0

 

[Radix]

The 50/60Hz sysgen selection does alter the number of absolute ticks per second, so some software could easily make (bad) assumptions and not behave as expected...