The 'major cycle interval' is determined by the logic design and implementation of the various different CPUs. In the PDP-8a logic print set are a couple of good timing diagrams of the minor state timing pulses, and what memory operations (read, write) are expected to occur during what timing pulses. There is a PDP-8e timing diagram as well, for comparison.
For the PDP-8e/f/m quad board set, the design of the bus timing is intimately tied to the capability of the core memory system available at the time. It basically determined how fast the CPU could run, as the PDP-8 does more or less one or two memory accesses per major cycle (ie, an instruction fetch read and a data read or write), or a data read-modify-write. The PDP-8 is basically a completely memory bound architecture (as are RISC based designs) but without a cache.
The PDP-8a is similar, it timing design is based on its memory system, and how fast the logic paths in its data/control paths could reliably run. I'm sure DEC would have made it run a lot faster if they could, but the restriction to one hex card, and the lower cost TTL logic of the day, dictated the 1.5us major cycle. I suppose DEC could have done a faster completely 74Sxxx schottky logic design, but it would have likely been power/cost uncompetitive in its design space.
