* after the last CLK fall, the low is held for 147uS. Data is kept at
the same level for 106uS. When attached to this PC clone, the data
line is drug low by the PC right after the CLK line goes low for the
last time, and then it releases it (and then the KB brings it low
after the 106uS mark.
Jim
I'm refreshing my memory re: the XT keyboard protocol, and because I made such great comments in my AT2XT implementation (and by that I mean barely any), I can't actually remember most of my sources of information. Do you still have your oscilloscope/signal traces?
Something is bothering me re: IBM's circuit. According to the block diagram on Page 4-4 in the 1984 IBM 5150 Tech Ref, one purpose of the keyboards' start bit is that it will eventually become the rising edge for IRQ1 when it reaches the LSB of the shift register. For the start bit to properly serve as the IRQ line, the shift register is expected to be clear (all zeros output) prior to clocking in data. When the start bit reaches the LSB of the shift register (8/9 bits total shifted in), the secondary LSB output feeds into a flip-flop (there are two outputs for the LSB- presumably the second one can be used for cascading).
Upon receipt of the next keyboard clock, the following things happen simultaneously:
- Flip-flop asserts IRQ1 (low-to-high transition).
- Shift register shifts in the last bit of the keycode.
- Flip-flop asserts an input on the shift register (~G) which causes the shift register to ignore new input and preserves old output (asynchronously- takes effect immediately).
- Flip-flop pulls-down the keyboard data line (asynchronously- takes effect immediately).
I can't verify this, but contrary
to this popular document, it seems
both clock and data lines are used to communicate statuses to the keyboard. CLK line low for an extended period resets the keyboard controller, and DATA line low says "PC is not ready for new data."
Setting PB7 of the PPI to 1 will clear the shift register to all zeros, and clear the flip-flop, which deasserts IRQ1, pulls up the data line, and deasserts the shift register input pin which causes the shift register to ignore data. Clearing PB7 will cause the shift register and the flip-flop to respond to the keyboard clock (according to the relevant datasheets for the TTL parts 74LS322 and 74S74, neither part will respond the the clock while CLR input is asserted).
Since the keyboard controls the clock line, this "down time" where PC pulls the data line low seems like a perfect time for the keyboard released the clock back high to the IDLE position without affecting the shift register/IRQ output. But according to your timing, this doesn't happen. Data line is released by the PC, implying the shift register/flip-flop was reset, before the keyboard releases the clock. I wonder why is that?
The other thing that bothers me is the following: indeed, the PC end will pull the data line low until the CPU clears the shift register and flip-flop, which in turn pulls up the data line. When you say and then "the KB brings it low after the 106uS mark", does this happen immediately after the PC stops pulling the data line low? Or is there a notable delay?
All references I've seen state that in "IDLE" position for the XT keyboard, data line is low, but that doesn't seem to be necessary, since the rising edge of the clock is what clocks in new data after the flip-flops are clear.
EDIT: I believe page 4-4 contains an error. PCLK (14MHz or so) should *not* be connected to the keyboard clock. The keyboard clock should feed into the D input of the nearest flip-flop.
