30 pin SIMM memory for RC2014 z80 Processor

[-N2]

Hi Everybody,

So as the title states I'm interested in rigging up some vintage 30-pin SIMM modules up to a z80, My initial thoughts are to use some programable logic as glue to the z80. Where the contents of the R and I registers are latched into the PLA and used to select between low/high memory space and one of 256 pages respectively. In theory that should provide 32 Megabytes of directly addressable space with some limitations.

To what end many of you might be asking yourselves, well my interest is in attempting to develop a preemptive multitasking OS. one where a hardware interval timer is used to interrupt the CPU and switch threads. With such a configuration one should be able to have 256 threads each with it's own compartmentalized 128KB of memory. I figure page ZERO would run the kernel that keeps track of everything.

Thoughts?

 

[Eudimorphodon]

Where the contents of the R and I registers are latched into the PLA and used to select between low/high memory space and one of 256 pages respectively. In theory that should provide 32 Megabytes of directly addressable space with some limitations.

I'm not really an expert on Z80 assembly so I guess it's not surprising I find this statement confusing; digging around I think I see where you're going with this, but I'm not really sure this has any actual advantage over just using a latch that's set by an OUT instruction. Both will have the annoying property that every time you switch pages you're swapping the whole memory map out; copying between pages is going to be a pretty big pain in the neck, and I don't think you're going to get any inherent advantage out snooping the values of these registers off the bus during the refresh cycle vs, again, just mapping a paging register to an explicit OUT command.

If you want more granular paging one obsolete option is the 74LS612; it's a little awkward to use with a Z80 in its full capacity because it has a *12 bit* data bus for loading the registers, but it can turn 4 address lines into 12 in one package, IE, let you access 16MB in 4K chunks. Another option would be to use 74LS670's; they only have 2 address lines, so you'll be using 16K pages, but a pair of them turns 2 address lines into 8 for 22 bit addressing, and adding a third will give you 26 bits. Of course you can probably implement the equivalent of a 74612 or a few 74LS670s in a decent-sized CPLD if you're going that direction already.

I've been kicking around ideas myself for how to implement paging for a kind-of-enhanced TRS-80 half-clone I've been sketching out for too long now, and I still don't have any fabulous ideas. Radio Shack's paging mechanism for the 128K Model 4 is pretty laughably simpleminded (Chunky 32k pages and a weird way to refer to them) and I'm not aiming for binary compatibility with it, so I'll probably just settle for a pair of 74LS670s or something. (I don't think I care about having more than 512K, or maybe a meg, or so anyway.)

 

[Plasmo]

I have a RC2014-compatible Z80 SBC design with DRAM but I didn’t use 30-pin SIMM but instead use a 2meg DRAM recycled from 72-pin SIMM. https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrc Since 2-Meg DRAM has very similar signals to 30-pin SIMM (minus the parity data and control), it should be easy to redesign the board for 30-pin SIMM. I ported CPM and Wayne Warthen’s ROMWBW to the board, but I have not thought of multitask OS.

I used CPLD as the DRAM controller and memory bank circuit. There are 64 banks of 32K RAM. It is easy enough to change it into 32 banks of 64K RAM, but bank switching may be tricky.
Bill

 

[-N2]

I am using this project as inspiration, the author does a great job explaining why linear addressing is superior to bank-switching small slices of memory. https://laughtonelectronics.com/Arcana/KimKlone/Kimklone_short_summary.html

 

[-N2]

I have a RC2014-compatible Z80 SBC design with DRAM but I didn’t use 30-pin SIMM but instead use a 2meg DRAM recycled from 72-pin SIMM. https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrc Since 2-Meg DRAM has very similar signals to 30-pin SIMM (minus the parity data and control), it should be easy to redesign the board for 30-pin SIMM. I ported CPM and Wayne Warthen’s ROMWBW to the board, but I have not thought of multitask OS.

I used CPLD as the DRAM controller and memory bank circuit. There are 64 banks of 32K RAM. Changing it into 32 banks of 64K RAM is easy enough, but bank switching may be tricky.
Bill

I've pondered if a small SRAM disk might help with that, making it accessible as an IO device rather than a memory. This way this scratchpad memory can be used while running code from any of the pages within a 32MB space.

 

[Plasmo]

I assume a mass storage device is essential to your multitask OS, so you can always count on having large temporary storage on the IO device. The other issue is when you switching out the entire 64K memory, you’ll need the exact same switching program located on the destination 64K memory bank. So how to install the identical switching program on all 256 banks is the challenge.

 

[Eudimorphodon]

I am using this project as inspiration, the author does a great job explaining why linear addressing is superior to bank-switching small slices of memory. https://laughtonelectronics.com/Arcana/KimKlone/Kimklone_short_summary.html

That's certainly an... interesting, project, but it's a doing a lot more than what you described in your first post. It's basically slapping a whole additional level of instruction decoding/microcode in front of the CPU to "auto-magically" switch pages and do other magic like switching back to the default page for anything that looks like a zero page or stack instruction. Shadowing the I and R registers would essentially be exactly the same thing as a plain page register, other than you'd be doing weird magic to snoop the contents of the internal registers in the CPU instead of making them discrete. There's no auto-increment or other useful behavior that you get from that shadowing.

I mean, gotta be honest, if 64K segments is what you want the 286 is a pretty decent CPU that'll run rings around any plain Z80, already has a 24 bit physical/30 bit virtual address space, and already has all the built-in needful for doing "far" memory accesses to things outside your current code/data segments...

(* Or, obviously, there are other Z80-with-wings CPUs that might be more up your alley? The eZ80 is an obvious choice...)

 

[Plasmo]

Jeff Laughton, aka “Dr Jefyll”, is a fixture on 6502.org and he is eager to explain the inner workings of using illegal instructions as co-processor instruction. He is also an outstanding & patience teacher.

To stay in Z80 family, you may be interested in Z280. In 8-bit mode it is compatible with Z80 yet its DMA and MMU can reach 16 meg memory space. It also have native 16-bit mode. I’ve designed RC2014-compatible Z280 in both 8-bit mode as well as 16-bit mode. My first Z280 implementation used 16-meg 72-pin SIMM as memory but all these memory is wasted on the relatively slow Z280 (12Mhz) so the current model only has 2 meg of DRAM.
https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:z280rc

8-bit Z280 SBC:
https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zz80mb:zz80mbr3

https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zzrcc

 

[-N2]

I have a RC2014-compatible Z80 SBC design with DRAM but I didn’t use 30-pin SIMM but instead use a 2meg DRAM recycled from 72-pin SIMM. https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrc Since 2-Meg DRAM has very similar signals to 30-pin SIMM (minus the parity data and control), it should be easy to redesign the board for 30-pin SIMM. I ported CPM and Wayne Warthen’s ROMWBW to the board, but I have not thought of multitask OS.

I used CPLD as the DRAM controller and memory bank circuit. There are 64 banks of 32K RAM. It is easy enough to change it into 32 banks of 64K RAM, but bank switching may be tricky.
Bill

Please tell me more about how you developed your CPLD, I'd like to try configuring one to interface with SIMM modules. SIMM and DIMM sockets can be sourced from here, https://www.peconnectors.com/sockets-pga-cpu-and-memory/hws9229/ for around $3 you can get a dual 30-pin SIMM socket.

 

[Plasmo]

Which CPLD are you familiar with? More importantly what do you have on hand since many CPLD are obsoleted. Ideally the CPLD should have large number of IO like 84-pin. If you can deal with SMT soldering, 100-pin or bigger CPLD is ideal. The other hardware issue is 30-pin SIMM which is limited to 16MB, but that’s hard to find. 4 MB is more common, but that’ll take 8 SIMM to reach 32MB total memory.

Design wise, you’ll need a bank manager to break 32MB memory into accessible banks like 32KB or 16KB; an address mux to merge large addresses into multiplexed row and column addresses; a refresh logic for CAS-before-RAS; and delay taps for generating correct RAS and CAS timings. It may sound complex, but a modest CPLD can accommodate them and still have room for other logics.
Bill

 

[bakemono]

My Z280 board uses 30-pin SIMMs with a DRAM controller inside an EPM7128. All of the timing is based on the Z280 bus clock. The first cycle is RAS precharge. The second cycle, the row address goes on the bus and RAS goes low. Because RAS is driven by combinatorial logic, it switches a few nanoseconds after the address. The third cycle, the column address goes on the bus and CAS goes low. Those are the read timings. For a write, WE goes low on the third cycle and CAS is delayed by a half cycle. This design limits how highly the DRAM could be clocked in general, but for the Z280 it gets the job done. I use standard refresh, with 9 bits of the address coming from the Z280 and 1 additional bit being counted inside the CPLD.

 

[-N2]

Which CPLD are you familiar with? More importantly what do you have on hand since many CPLD are obsoleted. Ideally the CPLD should have large number of IO like 84-pin. If you can deal with SMT soldering, 100-pin or bigger CPLD is ideal. The other hardware issue is 30-pin SIMM which is limited to 16MB, but that’s hard to find. 4 MB is more common, but that’ll take 8 SIMM to reach 32MB total memory.

Design wise, you’ll need a bank manager to break 32MB memory into accessible banks like 32KB or 16KB; an address mux to merge large addresses into multiplexed row and column addresses; a refresh logic for CAS-before-RAS; and delay taps for generating correct RAS and CAS timings. It may sound complex, but a modest CPLD can accommodate them and still have room for other logics.
Bill

I have this board, https://www.aliexpress.us/item/3256...t_main.85.4b4b1802qTdFH5&gatewayAdapt=glo2usa

 

[Plasmo]

Wow, good price. I have bought several at $8 each and made several retro projects with them. The biggest problem with EPM240 is 3.3V supply. Retro processors W65C02, Z180, 68SEC000, and 68EZ328 will work with 3.3V, but Z80 is marginally working at 3.3V. My solution was adjusting Z80 voltage to 3.5V so Z80 can run reliably at 16.7Mhz. Old 5V DRAM in 30-pin SIMM are less forgiving; my guess is they won’t run even at 3.5V, so you may need more modern SDRAM.
Bill

 

[-N2]

Wow, good price. I have bought several at $8 each and made several retro projects with them. The biggest problem with EPM240 is 3.3V supply. Retro processors W65C02, Z180, 68SEC000, and 68EZ328 will work with 3.3V, but Z80 is marginally working at 3.3V. My solution was adjusting Z80 voltage to 3.5V so Z80 can run reliably at 16.7Mhz. Old 5V DRAM in 30-pin SIMM are less forgiving; my guess is they won’t run even at 3.5V, so you may need more modern SDRAM.
Bill

Level converters are an option.

 

[-N2]

Which CPLD are you familiar with? More importantly what do you have on hand since many CPLD are obsoleted. Ideally the CPLD should have large number of IO like 84-pin. If you can deal with SMT soldering, 100-pin or bigger CPLD is ideal. The other hardware issue is 30-pin SIMM which is limited to 16MB, but that’s hard to find. 4 MB is more common, but that’ll take 8 SIMM to reach 32MB total memory.

Design wise, you’ll need a bank manager to break 32MB memory into accessible banks like 32KB or 16KB; an address mux to merge large addresses into multiplexed row and column addresses; a refresh logic for CAS-before-RAS; and delay taps for generating correct RAS and CAS timings. It may sound complex, but a modest CPLD can accommodate them and still have room for other logics.
Bill

What component do you suggest for 5-volt use cases?

 

[Plasmo]

If you mean 3.3V to 5V level converters, there are many available, but I don’t have real experiences with them. If you mean 5V CPLD, I myself use epm7128s, but they are obsolete and reliable sources are hard to find. ATF1508 is still in production, but programming tool is expensive (around $70) and development software (WinCUPL) is terrible. It is a difficult situation which is why CPLD is not used in most retro designs.

 

[-N2]

If you mean 3.3V to 5V level converters, there are many available, but I don’t have real experiences with them. If you mean 5V CPLD, I myself use epm7128s, but they are obsolete and reliable sources are hard to find. ATF1508 is still in production, but programming tool is expensive (around $70) and development software (WinCUPL) is terrible. It is a difficult situation which is why CPLD is not used in most retro designs.

This chip? https://www.aliexpress.us/item/3256804408416829.html?gatewayAdapt=glo2usa4itemAdapt I purchased that dev board, and a handful of the loose chips, figure I can use the eval board to test the chips.

 

[Eudimorphodon]

ATF1508 is still in production, but programming tool is expensive (around $70) and development software (WinCUPL) is terrible. It is a difficult situation which is why CPLD is not used in most retro designs.

WinCUPL is indeed... quite an experience. I use it when I'm working on *really* complicated GALs, where its simulation functionality is just too useful not to leverage, but it's bad and crashy and, worst of all, so archaic that it's hard to even install on modern Windows. I gather some people have had more luck than I have, but I ended up installing it on a Linux VM inside of WINE because it hated Windows 10 so much.

 

[Plasmo]

This chip? https://www.aliexpress.us/item/3256804408416829.html?gatewayAdapt=glo2usa4itemAdapt I purchased that dev board, and a handful of the loose chips, figure I can use the eval board to test the chips.

That’s a good chip to use and you’ve got the right strategy to test the loose chips. You may find some of the loose chips are not programmable, that JTAG interface is not working. That is a common problem encountered with used CPLD. EPM7128S can be designed with free Quartus tool (rev 13 or before) which is far superior to WinCUPL.

 

[Plasmo]

WinCUPL is indeed... quite an experience. I use it when I'm working on *really* complicated GALs, where its simulation functionality is just too useful not to leverage, but it's bad and crashy and, worst of all, so archaic that it's hard to even install on modern Windows. I gather some people have had more luck than I have, but I ended up installing it on a Linux VM inside of WINE because it hated Windows 10 so much.

I’ve done a few designs with WinCUPL in Windows environment, truly terrible experiences. One workaround is using a plain editor to enter design files then use WinCUPL only to compile the designs. At least that will avoid all these weird crashes.