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8080 memory interfacing vs z80

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alank2

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I've looked at the Z80 pins such as MREQ, IORQ, RD and WR and these make sense to me.


I'm now looking at 8080's equivalent and they are MEMR, INP, OUT, and /WO and these seem much less intuitive,

How do you know if it is a memory access? If BOTH INP and OUT are not active, then it is memory?

If it is a MEMORY, STACK, or OUTPUT WRITE, then WO is asserted, but yet MEMR is only for MEMORY or STACK reads?

It seems to me that the Z80 method is better thought out - is there some logic I am missing to the way the 8080 is designed?
 
The Z-80 bus is peripheral-centric. Which is nice because most of the things a CPU interfaces with are peripherals. 8080 and earlier CPU designs didn't have enough sillicon real estate yet to add those abstractions and their internal state machine was often exposed to the pins to allow for external support chips to perform that bus abstraction. I've not tried to understand the older chip buses in great detail as they can be a real PITA to get the logic just right.
 
Note that Intel 8086/8088 machines usually incorporate an 8288, which performs a roughly similar function breaking out the chip’s status and control lines into more user friendly signals.

I’m sure the Z80’s scheme was intentionally designed specifically to eliminate the need for a chip like the 8228; they were limited by the number of available pins so there aren’t completely separate memory and I/O R/W signals like you get with the Intel controllers, but they’re trivial to generate.
 
Of course, the 8086 had min and max modes. In min mode you could do away with the 8288 and the 8086 pins were much more simple at interfacing to the real world.

In max mode, you had to incorporate the 8288 to extract the status signals and the 8289 if you wanted to drive something like MULTIBUS.

Dave
 
To compare apples with apples, I'd say that the 8085 (introduced March 1976) and the Z80 (first samples in March 1976) are closer relatives than the 8080 and Z80. If you look at the interfacing for the 8085, it's quite straightforward; you don't need a system controller nor a clock generator. Small systems can be implemented using only three chips.
 
The 8085 does add the complication of needing an address latch to demux A/D0-7 unless you use specific Intel companion memory devices and peripheral chips. But in return you get dedicated prioritized interrupt lines that would require more complicated externals to replicate on the Z80.

I’ve always kind of assumed that Zilog also had the 6502 (public debut September 1975) at least somewhat in mind when they designed the Z80, with it also having a non-multiplexed bus and needing absolutely minimal external glue for a “simple” system with standard/generic memory.
 
Have a look at some 8080 and Z80 S100 CPU board designs to give you some insight on how the CPU signals generate S100 memory and I/O read/write signals.
 
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