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About re-producing PDP-11/70

The 2way associative cache of PDP-11/70 uses 256 x 1bit bipolar SRAM. The models I found are 74S201 and 74S301. Does anyone know of faster models with the same function？
 
I checked the engineering drawing of PDP-11/60 and found that its cache uses 93415A, which is indeed a 1K x 1-bit component with OC output. It also has a tri-state countpart component, 93425A.
They are all 16 pins, the same as 256x1bit components，but different pin layout.
Considering the cache structure of PDP-11/70, if 93425 is used, it is relatively easy to quadruple the cache capacity to 8KB, which is the same size as VAX11/780.
How do you think this is different from the original design? Or just using a quarter of the chip's capacity
 
alphaaxp said:
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Considering the cache structure of PDP-11/70, if 93425 is used, it is relatively easy to quadruple the cache capacity to 8KB, which is the same size as VAX11/780.
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So now you are going to start designing a PDP-11/72, eh?

Still very interested in what your backplane strategy is going to be. It is probably the most technically difficult part. The boards are all pretty straightforward.
 
The size, slot, and pin layout of the backplane are fully compatible with the original design. If possible, additional pins required for expansion boards such as PEP70/HC70 can also be added
If it is finally completed, I hope the new backplane can also work when inserted into the old circuit board
If the new circuit board is inserted into the original machine, there may be problems due to the lack of dec driver chips
 
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PEP70/HC70 went into empty slots (unwired). Part of the installation was to add power and ground to those slots…no other backplane signals. All signals were connected via ribbon cables that would have gone to the external memory boxes.
 
ggs said:
PEP70/HC70 went into empty slots (unwired). Part of the installation was to add power and ground to those slots…no other backplane signals. All signals were connected via ribbon cables that would have gone to the external memory boxes.
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Thank you, I will reserve power and ground for the empty slot
 
The read delay of the 256 x 1-bit chips found now is basically 40ns, and 93425A can reach 20ns
Considering the supply situation of chips, it may not be possible to achieve chip level compatibility with the original design, but there is no problem with board level compatibility
The current question is whether appropriate enhancements can be made to the design based on the chips used
Do you want to be completely faithful to the original version, or can you make some modifications?
 
For some (currently stalled) projects I was using 32K x 8 SRAMs that have an access time of 12ns (DIP and 5v). They weren’t particularly expensive either.
 
If that's the case, use the IS61C1024-12, a commonly used 486 cache chip, which is also 5V, 128K x 8-bit.
According to the cache structure of PDP-11/70, a 1MB cache can be achieved with only 11 chips(2way, [3bit tag, 3bit flag, 36bit data]x2=84bit), most of the boards may be empty, greatly reducing costs.
I always feel that this kind of replica is strange
What I am currently struggling with where is the boundaries of the changes?
 
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alphaaxp said:
I always feel that this kind of replica is strange
What I am currently struggling with where is the boundaries of the changes?
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What are *your* specific goals in this project? A replica is defined as a "exact copy"; you're already proposed to deviate from that in order to deal with IC supply issues. You've implied that module-level compatibility at the level of the backplane is a requirement. You've also implied that uCode should be unchanged. Those seem like two important boundary conditions since the latter requires that the ISP implementation be identical and the former requires that the functional partition of the implementation be identical.

Will extending the size of the associative cache be transparent to the uCode and have no effect on the functional partition? If so then it seems to be "allowable" according to your current realization rules.
 
pbirkel@gmail.com said:
What are *your* specific goals in this project? A replica is defined as a "exact copy"; you're already proposed to deviate from that in order to deal with IC supply issues. You've implied that module-level compatibility at the level of the backplane is a requirement. You've also implied that uCode should be unchanged. Those seem like two important boundary conditions since the latter requires that the ISP implementation be identical and the former requires that the functional partition of the implementation be identical.

Will extending the size of the associative cache be transparent to the uCode and have no effect on the functional partition? If so then it seems to be "allowable" according to your current realization rules.
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Expanding cache size is transparent and only involves M8143 and M8144

I hope to become a product that can be purchased and provide everyone with a real old style minicomputer experience in the future. It can also meet the learning objectives of computer organization, low-level integration, etc
The demand for collecting special models (Model 70 may be the largest PDP-11)

The modification of using high-capacity CMOS SRAM feels a bit large, and the board is too spacious
However, this idea may serve as an additional option after the machine is completed, just like the PEP70/HC70 did for the original PDP-11/70

I still haven't figured out whether it's 1K x 1-bit or 256 x 1-bit
 
If I understand correctly, does PDP-11/780 refer to VAX11/780 executing PDP-11 code in compatibility mode?
Most people don't consider VAX11/780 as a PDP11 sequence, and none of the FPGA implementations/simulators compare to it
 
alphaaxp said:
If I understand correctly, does PDP-11/780 refer to VAX11/780 executing PDP-11 code in compatibility mode?
Most people don't consider VAX11/780 as a PDP11 sequence, and none of the FPGA implementations/simulators compare to it
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I was simply pointing out that the series of "PDP-11" models includes the PDP-11/780. The native ISP is different, and although there is a compatibility mode that doesn't allow one to run, say, RSX-11. Again it's important to define your design constraints; so another seems to be to be able to natively run one or more of RSX-11, RSTS, etc.

By another interpretation of "large", the PDP-11/44 would be the correct choice since it replaced the PDP-11/70 and has roughly twice the performance (depending on your metrics of choice) ... and a *much* easier to implement memory subsystem.

I suspect that you have a fourth design constraint: that the model must include a traditional lights-and-switches front panel but I don't think that you've mentioned that anywhere.

IMO there are a limited number of hobbyists ready to mount and sustain an 18U 19" racked CPU. If your objectives include "provide everyone with a real old style minicomputer experience in the future" then IMO that's going to be a very small set of "everyone". I'd consider elaborating on what you define to be a "real old style minicomputer experience" given that it sounds like you intend to cut corners on I/O equipment (e.g., RM03) and memory (MJ11 or MK11).

I'm not criticizing; just trying to draw out and clarify your objectives and constraints.
 
pbirkel@gmail.com said:
I was simply pointing out that the series of "PDP-11" models includes the PDP-11/780. The native ISP is different, and although there is a compatibility mode that doesn't allow one to run, say, RSX-11. Again it's important to define your design constraints; so another seems to be to be able to natively run one or more of RSX-11, RSTS, etc.

By another interpretation of "large", the PDP-11/44 would be the correct choice since it replaced the PDP-11/70 and has roughly twice the performance (depending on your metrics of choice) ... and a *much* easier to implement memory subsystem.

I suspect that you have a fourth design constraint: that the model must include a traditional lights-and-switches front panel but I don't think that you've mentioned that anywhere.

IMO there are a limited number of hobbyists ready to mount and sustain an 18U 19" racked CPU. If your objectives include "provide everyone with a real old style minicomputer experience in the future" then IMO that's going to be a very small set of "everyone". I'd consider elaborating on what you define to be a "real old style minicomputer experience" given that it sounds like you intend to cut corners on I/O equipment (e.g., RM03) and memory (MJ11 or MK11).

I'm not criticizing; just trying to draw out and clarify your objectives and constraints.
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The traditional lights and switch front panel are indeed necessary for this replica machine.
Native PDP-11 implementation.

The reason for choosing PDP-11/70 is that firstly, I want a 70, and secondly, in the sequence of PDP-11, T11/F11/J11 is too similar to a PC, and most people may also be more interested in the 70

I also know that there are limited enthusiasts of models with 19 inch racks for this Unibus architecture, and I don't know if there can be 20 people to strive for cost balance in the world

The CPU/MK11 still has components that can be used, but the I/O part cannot be solved and must be reduced, as I cannot produce hard drives or tapes😅
The memory part will try to maintain the original style as much as possible, even with 1K x 1-bit chips, the number of chips is basically unchanged, except that the cache capacity has increased.

By the way, how much does a complete PDP-11/70 cost now without I/O included?
 
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