Aster CT-80

[Ruud]

In 1980 a Dutch firm created a clone of the TRS80, model 1: the Aster CT80. After more than 40 years there is not much technical documentation left and so I'm trying to create it myself. A lot is understandable except the refresh of the DRAMs.
I know how CAS, RAS and MUX are generated but I miss one thing: the refreshing address. How is guaranteed that the whole DRAM is refreshed within the specified time? A kind of loop, but where?

Then a question out of curiosity: why isn't the Z80's original refresh line not used, including the generated refreshing address? I know that this register has only seven bits = 16 KB but it IMHO it is not so much trouble to generate the 8th bit for 64 Kb DRAMs like the Aster uses.

Thank you in advance for any info!

 

[krebizfan]

The expansion bus includes the Refresh signal from the Z-80. If that was enabled, it might conflict with the memory controller on the ram disc board (and presumably other external memory boards). Just a guess based on the documentation.

Have you checked the ROM routines? That is where I would suspect the RAM to be cycled and accessed if the Z-80 or memory controller automatic refresh isn't used.

 

[Ruud]

Have you checked the ROM routines?

Unfortunately, no. With a little bit of luck I can access both machines coming Sunday and dump the ROMs. And then I have to disassemble them.

Haven't those of the TRS80 been disassembled yet?

That is where I would suspect the RAM to be cycled and accessed if the Z-80 or memory controller automatic refresh isn't used.

I have thought about this as well but isn't this a bit risky? It only takes someone to write a very small loop for what ever reason and, bingo, there goes your refresh.

 

[TRS-80.com]

Very nice page. I have put a link to it on the Clones page on TRS-80.com

There is no method in the TRS-80 ROMs to refresh RAM chips. I am not even sure how such a thing could be possible in a ROM.

 

[kkaempf]

The TRS-80 Technical Manual (page 12, 14 in the pdf) has a section on "refreshing the rams":
"The dynamic RAM in the TRS-80 uses ''/RAS only' type of refresh. In other words,
when RAS* goes low, the RAMs in the system will 'refresh themselves' even though
the RAM may not be in use at the time"

Hth,
Klaus

 

[krebizfan]

The Custom TRS-80 has a description of the Model I's refresh circuit on page 44. I don't know if the Aster uses the same method. Page 45 shows some interesting RAM addressing information; not exactly necessary to the refresh topic but too strange to go unremarked.

MREQ does the RAS while the master clock plus RD and WR lines gives a CAS signal and MUX to switch from row to column. It is not clear to me how the Model I moves through the entire address space for the refresh.

 

[Ruud]

The TRS-80 Technical Manual (page 12, 14 in the pdf) has a section on "refreshing the rams":
"The dynamic RAM in the TRS-80 uses ''/RAS only' type of refresh. In other words,
when RAS* goes low, the RAMs in the system will 'refresh themselves' even though
the RAM may not be in use at the time"

But these type of RAMs don't have an internal refresh circuit and need an external address. The "CAS-before-RAS" ones do have this circuit.

The Custom TRS-80 has a description of the Model I's refresh circuit on page 44. I don't know if the Aster uses the same method.

Yes, it does. And that's why I turned to you Tandy-fellows, hoping you could tell more.