I have one of the Cirtech CP/M boards that plugs into the 6502 socket for the //e. I have disassembled all of the non-DRI bits and there is some copy protection in there that uses the 6502 <-> Z80 address PROM and the A11 line to check it's running on the right hardware.
While this is fine for the //e version and I have commented out the protection for the //e to allow running in emulators. the IIGS version of the Cirtech CP/M system doesn't boot on my hardware. Thanks to some work by someone else (via the AppleWin emulator github issues) we know that again address translation is involved for the IIGS version (which plugs into a slot). I'm looking to add both versions of the Cirtech card to AppleWin, I could hard code the address swaps for the IIGS version into the system, but from looking at both the //e and IIGS code I suspect some of the hardware versions latch the A0,A1 address lines on the Z80<->6502 processor swap addresses and feed them into the address translation adder (or one of the lines on the address translation PROM) which probably improves Softcard compatibility compared to the //e version I have.
I have some code for the CP/M side of the system that exercises this address latching functionality, is there anyone with one of the Cirtech IIGS systems that can boot the V2 of the Cirtech CP/M plus system who could run this test code on real hardware and report back? (I have DM to one person who might be able to help)
While this is fine for the //e version and I have commented out the protection for the //e to allow running in emulators. the IIGS version of the Cirtech CP/M system doesn't boot on my hardware. Thanks to some work by someone else (via the AppleWin emulator github issues) we know that again address translation is involved for the IIGS version (which plugs into a slot). I'm looking to add both versions of the Cirtech card to AppleWin, I could hard code the address swaps for the IIGS version into the system, but from looking at both the //e and IIGS code I suspect some of the hardware versions latch the A0,A1 address lines on the Z80<->6502 processor swap addresses and feed them into the address translation adder (or one of the lines on the address translation PROM) which probably improves Softcard compatibility compared to the //e version I have.
I have some code for the CP/M side of the system that exercises this address latching functionality, is there anyone with one of the Cirtech IIGS systems that can boot the V2 of the Cirtech CP/M plus system who could run this test code on real hardware and report back? (I have DM to one person who might be able to help)