Commodore PET - Multi-EditorROM + 40/80 Column Switcher

[ngtwolf]

Hi All,

Question, but first a bit of a backstory. Picked up a Commodore Pet 4032 a few years back that was modded to be an 8032. It had some ram issues and I fixed those, but I left it as an 80 column. Recently I picked up the following board and figured i'd put that in so I'd have both options ( http://www.6502.org/users/sjgray/projects/multied4080/index.html ). To play it safe, I cleaned up all the old wirewrap that was on there, put some modern pin headers (or pin sockets) in the appropriate place, and reverted it back to 40 column. There was some challenges in that since it turns out there was an issue with one of the video ram LS chips, and there was some terrible butcher soldering that was done in the past I had to clean up.. but eventually got it all working in 40 column. The interesting thing is that it doesn't work in 40 column at all with UB8 socketed (even with pin 1 disconnected) which seemed odd since this blog ( http://blog.tynemouthsoftware.co.uk/search?q=40+80+column ) about reverting seem to imply that he originally left UB8 socketed and didn't have an issue, but he did pull out the ram so who knows).

Now fast forward to my problem. I can easily swap between 40 and 80 columns by changing the jumpers and the roms (and adding UB8 for 80 column) but whenever I hook up the board i just get garbage whether having it at 40 columns or 80 columns using standard 40 column and 80 column CRTC N keyboard roms. I'm 1) curious if anyone has even used this board - maybe there's something wrong with it (there were some typos in the instructions that I caught) and if anyone has, maybe they have some suggestions to look for. Incidentally i'm using the MER-SET-03-N-Keyboard bin on here (https://github.com/sjgray/Multi-EditROM-Builder/tree/master/ROM_Sets), if that matters.

Thanks for any help!

 

[Eudimorphodon]

I'm looking at the schematics on zimmers.net, and for both the "univ" and "univ2" boards it looks like pin1 of UB8, latch for the "odd" VRAM, is tied directly to CLK1B, which means it's always going to be asserting on the bus between the latches and the character generator, while pin one of UB3, the "even" latch, is tied to ground (always enabled) for 40 columns and tied to CLK1 for 80 columns. If this is right, IE, there's no jumper for cutting off CLKB from UB8, then, yeah, you're going to have bus contention in 40 column mode, guaranteed.

Pin 1 on UB8 should *probably* float high if you have it out of the socket, but that's not necessarily a sure thing; have you tried holding it high with a pull-up resistor? This should prevent the contention, but... yeah, if the schematics are correct it seems like leaving this device present in 40 column mode would be a no-no unless you pulled a pin/cut a trace/whatever to make it possible to shut it up.

... although, wait. What happens if you leave JP5 set for the 80 column position while having everything else set for 40 column mode? I'm looking at sheet 6, specifically how the shift register load is timed, and wondering if having JP5 in 80 column mode (but moving JP3 for 40 column) will fix the buffer contention while still allowing 40 column text to work.

 

[ngtwolf]

It was a bit hard to follow what you were recommending and which problem you were trying to help solve. I -think- your suggestion was for how to leave UB8 in while in 40 column mode and if so, I tried connecting JP5 and leaving UB8 in and connected and it just gives a black screen.

Either way, I can get 40 column to work fine by just removing that chip, and 80 column by adding the chip back, and if i intend to leave it in either mode then that's not a big issue either way. The main thing I was trying to do was to get this 40 80 column multikernal switcher board to work, which would allow me to easily switch between 40 and 80 column (and different kernals) by just flipping the dip switch to whichever of the 16 kernals i want (or possibly adding a switch in the back and switching that way), however this board doesn't seem to work (it gives garbled screen no matter what mode/kernal i'm using) so i'm not sure if it's a problem with this board that i did wrong, or if it never worked, or if someone else had built one of these and knows what might be happening (maybe something was wrong in the build docs or schematics).

 

[Eudimorphodon]

It was a bit hard to follow what you were recommending and which problem you were trying to help solve. I -think- your suggestion was for how to leave UB8 in while in 40 column mode and if so, I tried connecting JP5 and leaving UB8 in and connected and it just gives a black screen.

That's interesting, because it my interpretation of the schematic was that if the other jumpers are in the 40 column position having JP5 should relieve the interference from a "present" UB8 at the cost of only having the buffer contents asserted to the character generator for half the (longer) character cadence. (The other half of the cycle will have junk from UB8 asserted. Which... would either be a fatal flaw or possibly okay, depending on when the shift register latch pulse happens.) Just to asked the obvious, you disconnected JP6 for this test?

Either way, I can get 40 column to work fine by just removing that chip, and 80 column by adding the chip back, and if i intend to leave it in either mode then that's not a big issue either way. The main thing I was trying to do was to get this 40 80 column multikernal switcher board to work, which would allow me to easily switch between 40 and 80 column (and different kernals) by just flipping the dip switch to whichever of the 16 kernals i want (or possibly adding a switch in the back and switching that way), however this board doesn't seem to work (it gives garbled screen no matter what mode/kernal i'm using) so i'm not sure if it's a problem with this board that i did wrong, or if it never worked, or if someone else had built one of these and knows what might be happening (maybe something was wrong in the build docs or schematics).

I'm looking at the build instructions for that board and, sanity checking here, did you run the wires which selectively bypass UB8 pin 1? The fact that this board includes this verified that you *must* either remove UB8 or tie pin 1 of it high to run in 40 column mode. If you already ran this bypass you could add a toggle switch that either connects it to its socket point or pulls it high with a pull-up resistor.

 

[ngtwolf]

That's interesting, because it my interpretation of the schematic was that if the other jumpers are in the 40 column position having JP5 should relieve the interference from a "present" UB8 at the cost of only having the buffer contents asserted to the character generator for half the (longer) character cadence. (The other half of the cycle will have junk from UB8 asserted. Which... would either be a fatal flaw or possibly okay, depending on when the shift register latch pulse happens.) Just to asked the obvious, you disconnected JP6 for this test?

Yeah, JP5 connected and JP6 disconnected with UB8 Installed and pin 1 either connected or disconnected gets garbage. JP5 connected and JP6 disconnected with UB8 removed, interestingly works but everything is inverse.

I'm looking at the build instructions for that board and, sanity checking here, did you run the wires which selectively bypass UB8 pin 1? The fact that this board includes this verified that you *must* either remove UB8 or tie pin 1 of it high to run in 40 column mode. If you already ran this bypass you could add a toggle switch that either connects it to its socket point or pulls it high with a pull-up resistor.

For UB8, the pcb/pin wires are run to the board (black and white wires on the PCB). The board theoretically controls pin #1, which is honestly what's confusing to me as that implies the pcb should control whether UB8 is activated or not by controlling that pin, but clearly that's not the case because UB8 socketed at all would cause garbage when in 40 column mode. I guess what confused me further is that the design of the pcb implies that UB8 can be socketed and be controlled by pin 1, and that the tynemouthsoftware link where he reverted to 40 column and didn't remove UB8 also implies that UB8 can be socketed and still works with 40 columns, but in my case, 40 column isn't working with it socketed and that pcb doesn't even work. Though, to be fair, in tynemouthsoftware link, he did remove the socketed vram for 80 column, but i just tried that as well since i had socketed those, and it made no difference.

Again, it's not the end of the world either way, worst case I'll remove UB8 and leave it as 40 column because that's really the best setup overall.. It's just confusing me that things that seem like they should work aren't. Or rather, how other people portrayed them working, doesn't.

 

[Eudimorphodon]

For UB8, the pcb/pin wires are run to the board (black and white wires on the PCB). The board theoretically controls pin #1, which is honestly what's confusing to me as that implies the pcb should control whether UB8 is activated or not by controlling that pin, but clearly that's not the case because UB8 socketed at all would cause garbage when in 40 column mode.

UB8 shouldn’t interfere if pin1 is held high, IE, it *should* be functionally equivalent to pulling it out. The reason the board runs two wires to pin1 (one to the PCB, the other to the pin on the chip itself, is to provide that gating. (IE, in 40 column mode the chip’s pin1 should always be high, while in 80 column mode the pulses from /CLK1B signal on the PCB should come through the buffer to the chip.

Do you have a scope, or even just a logic probe, to see if the board is actually toggling that function correctly?

 

[ngtwolf]

Got sidetracked on this but circling back. I’ve identified and fixed the issue with the UB8 chip. It was faulty, which caused problems regardless of pin 1 connection. While the board works fine in 80-column or 40-column mode, it still doesn’t function with the 40/80 column switcher board.. As an aside, pin 1 can be connected for 40 column mode if the two ram chips for 80 column are removed (as they were on that blog post), so that also explains why he was able to run it with UD8 socketed, because he had pulled out the ram. Anyway, I'm still trying to figure that out, but at least this solves the problem with UD8. I'll give it another week to figure this out, and if I can't, i'm just wiring it up for 40 column and moving on to other projects..