Compaq Proliant 1500

[Scruit]

Hello all,

Still occasionally breaking out the Compaq Proliant that won't POST, and mapping out the board looking for a reason.

History: Proliant 1500 Dual P166. On power up there is no sync to the VGA, no post, POSTCard shows nothing at all ("-- --"). The ISA address/data lines show a burst of activity for around 10-20 seconds before ceasing. Clock lines looks goos to a certain extent... Some things get the expected clock signals and some don't. BIOS Rom, specifically, gets not clock/data/address acticvity. Even with the ROM removed, there is no activity so it's not a shorted ROM pulling the clock/address/data low.

Current testing: I am testing the EISA chip, and the PCI-EISA bridge associated with it. These get the expected clock signal IN but are not producing the expected clock signals out (one pin goes direct to the BIOS ROM).

Then I noticed the reset line is being held high all the time. Oscilloscope trace shows that the reset line goes low when the system is powered off, and on powerup it goes high and stays there. This does not appear to be a reset-on-low signal like a C64 or similar. The EISA chip datasheet says "When asserted" the chip going to reset state until rest i no longer "asserted".

So my next steps are to understand what is driving the rest line high. I already tested the power-good line from the PSU so I know the PSU is trying to start the board.

Anyone got any experience / ideas / links that would help me understand the sequence of events that a pentium motherboard would go through before choosing to drop the reset line and let the system boot up?

 

[modem7]

The EISA chip datasheet says "When asserted" the chip going to reset state until rest i no longer "asserted".

As an example, the RESET signal throughout the IBM AT motherboard is shown at [here].
In some cases (e.g. RESET for 80286), the RESET signal going about the motherboard is 'active high', i.e. RESET is 'asserted' (happens) when that signal is high.
In other cases (e.g. RESET for keyboard controller), the RESET signal going about the motherboard is 'active low', i.e. RESET is 'asserted' (happens) when that signal is low.
So in measuring the RESET signal about the IBM AT motherboard, I need to be aware that sometimes I am to expect a low, and sometimes to expect a high.

I presume that you are monitoring the RESET pin on an EISA chip, and the chip's datasheet indicates that the pin is 'active high'.