• Please review our updated Terms and Rules here

Connecting logic outputs in parallel

RobS

RobS

Experienced Member
Joined
Sep 28, 2012
Messages
293
Location
Kent, England
In my Honeywell 200 replica project I have a problem that might need my design to sail close to the wind. I am using original Honeywell logic ICs from the 1960s that are probably DTL and the maximum fanout of the outputs is ten standard inputs. However, my design often requires a signal to go to sixteen input gates. I could double up on the output gates to provide for twenty input loads in total, but that would require using extra pins on the PCB edge connectors and there are never enough of them to do this. The question is whether I could connect two outputs to a single logic line to avoid needing an extra pin. It normally isn't advisable to connect transistors in parallel in this way unless they are thermally closely connected and otherwise similar, but my ICs each contain two similar gates on one chip, so maybe they do meet those requirements. Certainly the output pins on the ICs are close together, which suggests that the output transistors are too on the chips, so thermally very closely connected. If I connect all the corresponding inputs to the two similar gates in parallel as well then the IC ought to behave as one gate with twice the fanout ... maybe.

The signals are at conventional five volt logic levels, so maybe a precaution would be to include a small resistor at each output to help balance the current evenly without the voltage lost causing too much detriment to the noise immunity. Also perhaps testing the outputs at full current capacity to determine whether they are closely matched in particular ICs would be a good precaution as there could be manufacturing differences even between transistors on the same chip. If the voltage differences between the two outputs with the same current at any temperature are negligible then the currents are likely to stay balanced at all temperatures, I assume, but maybe a long soak test at full load would be needed to check this.

Another option that I have is to build output driver circuits using more powerful discrete transistors, but that would probably increase the propagation delays for the signals unless I build the entire DTL logic gates using discrete components, which would take up much more space on the PCBs. The original Honeywell 200 did use discrete components throughout, not these ICs which were introduced in another model, the 120, a few years later in the decade, but the H200 used twice as many backplanes as I have, so I need to put as much logic as I can on each PCB to save space. I'm keeping to Honeywell's convention for the number of ICs per PCB though, so I'm not crowding them, but the pin limited edge connectors were designed for use with far fewer logic gates per PCB constructed with discrete components, so those legacy edge connectors are always bottlenecks in my design.

Does any experienced circuit engineer have an opinion on this?
 
DTL didn't use active pullups, so you're safe in paralleling outputs; as a matter of fact, it was common practice to "wire OR" outputs on DTL and RTL--something forgotten since TTL days because almost all TTL uses totem-pole (push-pull) output.

However, I'd probably look for a DTL "power gate", such as the 844 or 857, which have fanouts in excess of 25 loads.
 
Chuck: Thanks for your remarks, but they aren't really applicable to my situation.

For my machine to be regarded as being in the style of the 1960s Honeywell 200 range, even if it is only a pastiche, I am restricting myself as far as is practical to using components that I know Honeywell used during that decade in their machines. For that reason I am only using their own ICs and transistors from that decade. As a demonstration of my pedantry, I know that they started using AGNA1 monostable timer ICs (equivalent to the 9601) in place of timers constructed from discrete components some time around the end of the 1960s or start of the 1970s, but I need to confirm the precise design dates for the specific logic modules involved before I commit to using those ICs in my design. I have no evidence that Honeywell used IC power gates as drivers. They appear to have resorted to discrete transistor circuits wherever higher fanout was needed.

I suspect that the design of the Honeywell ICs closely followed the design of their previous circuits built with discrete components but I don't have the internal schematics for the ICs to verify this. I have schematics for some of the discrete circuits and a striking thing about the later ICs is that they employ external feedback capacitors to regulate the rise time of the outputs in exactly the same way that the transistor output stages did. There are specific feedback pins for this purpose apart from the normal inputs.

My tests on the ICs indicate that their outputs have a strong pull-up capability, probably active rather than resistive. Looking at the evolution of the equivalent discrete component modules, series three used pullup resistors in the output stages but the later series five used totem pole transistor stages. I referred to the ICs as probably being DTL because in the discrete circuits the inputs always used diodes rather than directly going to transistors, but I don't know what they are really. Certainly their outputs are powerful enough to be used as modest current sources, not just sinks, which I have actually done in some temporary test rigs, so it's highly unlikely that they can be wire or'd. In fact the range includes specific ICs that do provide wired or output and input connections for building large custom gates, but these can only be used together and not connected to the standard inputs and outputs. The normal ICs obviously have two transistor stages in them to eliminate inversion of the signals and the wired or connections appear to be special links to points between these as they are inversions of the normal logic.

Hence my question was actually about the wisdom of paralleling totem pole outputs, which can only succeed if the two similar gates on the chip behave in exactly the same way with exactly the same responses to the paralleled inputs. It didn't occur to me that DTL is always assumed to have single ended outputs rather than totem poles, so I may have been misleading there. I thought that was only a characteristic of RTL.

Working with these Honeywell ICs I've had to disregard my assumptions about mainstream IC development as they are unique in my experience with their special feedback and wired or connection points. The only thing that I can be sure of is that they have transistors in them somewhere that behave normally.
 
Totem pole outputs are essentially constant current sources. I see no issue with paralleling them if they have the same input signal and use the same package. When pulling down, it is more of an issue for balance but with both on the same silicon it should work. My rule that has worked well in the past for both ICs and connectors in parallel is to multiply the individual current by 2 and then by the square root of two. Using 16 is a little on the outside of that rule that would say 14 is a safer number of loads to share. Of course small resistance will help sharing more.
I was looking at connectors in parallel for power supplies. We saw connectors fail in parallel when exceeding this and working well when less then. It was based on a lot of connectors and measuring currents with a hall meter. The rule seems to work well for more connections, like 3 connector total divided by square root of 3. Why it worked I don't know as it was by experiment with connects af 50 to 100 amps.
Dwight
 
RobS said:
.....a striking thing about the later ICs is that
they employ external feedback capacitors to regulate the rise time of the outputs
in exactly the same way that the transistor output stages did. There are
specific feedback pins for this purpose apart from the normal inputs...
Click to expand...

Rob....Would you please explain the significance of the rise time..?

Thank you

ziloo :mrgreen:
 
Dwight Elvey said:
Fast rise and fall times cause reflections of unterminated lines, power supply noise and possible cross talk.
Click to expand...

Chuck(G) said:
I still don't quite understand why a power gate or buffer won't be used to accomplish the end. All logic families have them.
Click to expand...

How about "level sensitive" and "edge sensitive".......... do these also apply to
computer designs with discrete components?

ziloo :mrgreen:
 
Depends on the implementation. But yes, there were several implementations using capacitive coupling, which is essentially, "edge sensitive" logic.

Details on the logic family being used are important.

Bipolar TTL is current-driven with what amounts to "negative" logic--circuit drive capacity is stated as the ability to "sink" current, not to source it. CMOS is voltage-driven, so while fan-in current is tiny, voltage levels must be observed with attention to capacitive loading. Vacuum-tube logic essentially follows CMOS. There are many variations--and many all-but-forgotten logic families. ECL is probably still used in a few applications; RTL, HTL, DTL, DCTL, etc. are probably hard to come by.
 
One problem with fast rise times is that if there are a lot of loads spread along a wire, the miller feedback can cause a double clock towards the end of the wire. It usually takes a lot of loads. This is usually avoided by placing a small resistor in series with each load. That slows the signal and minimizes the effect of the miller feedback.
I don't think level or edge has an effect except the case I pointed out where there are a lot of loads.
Dwight
 
I'm more used to seeing Miller effect issues on high-impedance stuff like CMOS or vacuum tube equipment. I suppose if a lead is long enough on a low-impedance TTL output, it could happen, but I've never seen it.
 
Chuck(G) said:
I still don't quite understand why a power gate or buffer won't be used to accomplish the end. All logic families have them.
Click to expand...

Under my self-imposed regime I can only use the technology that I have in the boards that I salvaged or others that I find in the future and in over a thousand boards there were no power ICs at all, so I have to assume that Honeywell used only transistors for this purpose. The "family" of ICs in those Honeywell boards extends to just seven different IC types with a couple of odd ICs that indicate that there was actually an eighth type which may have been phased out. Although made by regular IC manufacturers such as Texas they appear to be specials made for Honeywell, so not part of any regular production family. My project is about sticking to Honeywell's house style from that era and only using their stock components. I doubt that their technicians would have cheated by paralleling outputs, but I would have back then. If I start using other ICs then I may as well use a Raspberry Pi and save myself a whole lot of work.
 
I simply didn't understand that you were trying to use old stock exclusively.

What are the switching speeds on this stuff? Would using a darlington as a driver be considered cheating?
 
Chuck(G) said:
I simply didn't understand that you were trying to use old stock exclusively.

What are the switching speeds on this stuff? Would using a darlington as a driver be considered cheating?
Click to expand...

I tested the switching speed by chaining six gates in series to get an overall delay that was easy to measure and this test yielded on average 20nS per gate with Honeywell's commonly used 33pF feedback capacitors to control the signal rise time on each gate. In their documentation they refer to this configuration as "slow gated buffer amplifiers" so I assume that they also used the ICs elsewhere with smaller capacitors to run as faster buffer amplifiers. I have seen 22pF used in some of their circuits and in a few places where an output connected directly to an adjacent input on the same PCB the capacitor was omitted entirely. In my PCB designs I have made provision for the feedback capacitors but have not installed any between on board interconnections initially. The normal clock speed of the circuits is 4MHz, so depending on the length of the logic chains I have some leeway for switching delays. Having control over the signal rise times on individual gates is an added dimension to the design of IC logic circuits to which I am not accustomed and I may need to experiment with tweaking the capacitor values on individual circuits to ensure reliable operation.

Tweaking is the order of the day with this old Honeywell technology. The main magnetic core memory unit, which is Honeywell's original design using transistors throughout, has fifty-two trimming pots to tweak as well as feedback capacitors which have to be changed to set the right signal rise times. Fortunately someone in Switzerland sent me a copy of the original thirty page instruction manual on tuning up a newly built memory unit of this type, so I have Honeywell's set procedure to follow. When it comes to my own IC circuit designs I will just have to see what happens though. Currently I am giving serious thought to the layout of my logic modules on the backplane to get the optimum combination of wire lengths between them, which is also likely to be a factor in choosing those feedback capacitors. So, the answer to your question is that it all depends on many factors.

Honeywell certainly used transistors in Darlington pair mode for power drivers including some indicator light circuits, such as for the lights on the iconic H200 control panel. I will have to copy that approach for some of my signals, but having to do it for just sixteen unit loads is a nuisance when a normal gate can drive ten. If I can spare the edge connector pins I will just feed the output from two gates to eight loads each separately and not parallel them onto one pin.
 
You must log in or register to reply here.
Back
Top