DCJ11 HALT not working

[acebritpilot]

Hi, this is my first posting here! I have been trying to get a DCJ11 / PDP-11 hack working, copying Hilpert's PDP-11 hack (discrete TTL not GAL), and I'm using stripboard not breadboards.
However, I'm stalled as the J11 doesn't HALT so I can't get into the octal debugging interface. I'm pretty sure the wiring is correct, and the HALT pin 9 gets 0-5V (the reset works and sees 5V-0).
It's kind of looking as if the J11 is faulty (from China, supposedly new in a DEC box) but is there any other possible reason why the J11 won't halt after reset?
A few pins such as DA1 have a signal running constantly after reset despite halt being +5V. I'm using a 4MHz xtal. Any ideas welcomed!

 

[cbscpe]

Hilperts Version does not have a configuration Register during start up and the configruation of boot mode, FP presence and HALT behaviour is rather random. In most cases some high (4k7 resistors) value pull-ups and downs on DAL0,1,2,3,8 should help. See also the Semiconductor Manual from DEC.

 

[acebritpilot]

Hilperts Version does not have a configuration Register during start up and the configruation of boot mode, FP presence and HALT behaviour is rather random. In most cases some high (4k7 resistors) value pull-ups and downs on DAL0,1,2,3,8 should help. See also the Semiconductor Manual from DEC.

Thanks! Is that each of those DAL lines has both pull up and down (putting it halfway)? Apologies if that’s incredibly dumb….!

 

[acebritpilot]

Thanks! Is that each of those DAL lines has both pull up and down (putting it halfway)? Apologies if that’s incredibly dumb….!

Ah yes, it was dumb. You mean setting 1 or 0 according to the power up config. I guess bit 8,3,2=0 and 1,0=1? It now does seem to power up halted but thereafter, if I do init=0 + halt=1 it runs off as soon as init goes high, the halt (pin 9) seemingly unresponsive

 

[cbscpe]

Exactly putting a pull-up or pull-down on DAL8,3.2.1,0 accordingyour needs. What do you mean with "if I do init=0 + halt=1"? Make sure INIT to the DCJ11 has proper level changes, don't use a just a switch. At least have a small capacitor to debounce the signal. A RS-Flip-Flop is recommended.

 

[daver2]

As these are your first posts, welcome to VCFED.

I fully agree with all the above.

Which schematics are you using (out of interest)?

The earlier schematics had a problem with byte writes (as detailed on the original schematics) and (as has been stated) the power up register and debounce.

Dave

 

[acebritpilot]

As these are your first posts, welcome to VCFED.

I fully agree with all the above.

Which schematics are you using (out of interest)?

The earlier schematics had a problem with byte writes (as detailed on the original schematics) and (as has been stated) the power up register and debounce.

Dave

Thanks to everyone for the helpful advice! I will definitely try providing better init and halt signals rather than just a switch and pull up/down. The schematic I used are the ones pdp-11/hack dated 2014 may 24, so discrete ic’s not the gal version. Of course there maybe much better versions but if I’d can get the thing to halt at least, worth exploring further. Let’s see how denouncing those two signals goes! Thanks!

 

[daver2]

That version (as the text states) does not perform a byte write to memory correctly. It still performs a word write. So the 'xxxB' instructions (that perform a write) will misbehave.

We discussed the fix for this problem (if I remember correctly) in a VCFED thread if you fancy a "hunt".

I will see if I can remember the fix...

EDIT: See thread here: https://forum.vcfed.org/index.php?threads/pdp-sbc-j11-hack.55374/.

Here is the outcome from the thread: https://www.chronworks.com/J11/.

Dave