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EOI: XLR8er redesign/reverse-engineering/work-alike (or alternative speedup board)

L

lowen

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One of the nicest addons to the TRS-80 Model 4 and 4P was definitely the H I Tech XLR8er. Misosys closed these puppies out at really low money back in the day, but I remember an auction on eBay last year some time where an XLR8er fetched $500 (twice its original selling price!). Now, I'm glad Ian got the proceeds from that; he has done a lot for the TRS-80 community.

Now, I'm gauging interest in a rework of this board. I say 'rework' because I am not really interested in making a 100%-true-to-original-using-80's-FR4-PC-stock-and-original-period-correct-chips replica to cater to collectors (or to people who want to try to pass off a replica as an original); I am interested in something more in line with the spirit of FreHD, M1SE, M3SE, etc. Although, if I had a non-functional XLR8er in-hand I am capable of reversing the schematic and as long as it's not multilayer I can reverse the PC layout. I wouldn't want to work on a functional unit, though, since they really are quite rare, but I could. And I would give it back to you, and maybe throw in something extra for the loan of the XLR8er (like maybe a CPU280 kit......).

Matt Reed states in his article on TRS-80.org on the subject that the XLR8er design was based on Ciarcia's SB-180. I'm not sure where he got that information, but it seems reasonable. I have found one photo of an actual XLR8er (from dr_ians_junque's eBay listing last year; I downloaded it last year while it was still listed), and the chip layout is found in the XLR8er manual found on Tim Mann's website. If indeed the design was based on the SB-180, then it shouldn't be too hard to reverse-engineer the schematic based on the SB-180's schematic (available in the Byte article series on the SB-180) and the actual XLR8er's layout (which has the chip numbers, which likely would be performing the same function on the XLR8er as on the SB-180).

A new design would be quite different: first, I would use the 68-pin PLCC version of the Z8S180 with a through-hole socket. Second, I would use one or two AS6C4008 512Kx8 55ns static RAM chips instead of DRAMs, which would eliminate some of the chips used. Third, I would put in a cycle-stretcher circuit so that the Z8S180 chip could run at a much higher clock speed accessing its local RAM, while still accessing the Model 4 system at 4-5 MHz (the XLR8er runs at 6.144MHz, and it doesn't look like too much bus interfacing is being done to downshift, except perhaps an extra WAIT state or two). The Z8S180 can officially run at up to 33MHz, with a few brave souls pushing it up to 49+MHz on the P112, based on the Z182 chip). The Z8S180 can run at any speed less than its rating; it has a static core, and can even be completely stopped. So running a 33MHz-rated Z8S180 at 6.144 or other lower speed is ok.

However, I have to think about alternatives to the Z180 line for a speedup board, including the fabled Z280. Anitek had a Z280 replacement board in the works, the TRX-280, but ran into all sorts of issues (none of which are documented that I know of). Z280's are not unobtainium these days; UTsource has the chips in quantity, and I personally have about 20 of them on-hand for production of my reproduction of the Reh CPU280 board. But the Z280 is limited to 12.5MHz, and is rather buggy. But, if you want that kind of challenge..... one bug in particular is a deal-breaker for a drop-in Z280 board for a TRS-80; it seems that any I/O write operation must not be immediately followed by a JP, JR, CALL, or RST operation or the chip can do Bad Things. This means any TRS-80 program that uses any OUT-family instruction has to be modified to make sure that no JP-family instruction follows (need four (4!) NOPs or an IN between). So I've decided that having a CPU280 eventually running a ported LS-DOS 6 would be preferable to trying to build a Z280 drop-in upgrade. And, let's face it: no software currently exists in Tandyland that can use the Z280's wonderful new addressing modes and instructions. Again I would recommend that if you just have to have a Z280 computer you need to build a CPU280, which is a tested and proven design and readily buildable.

The two other alternatives are the Z380 and the eZ80. Now, Z380 chips really are unobtainium these days, and they weren't socketed like the Z280 could be, so they're not easy pulls. The eZ80 would be cool (if only for the possible name: TReZ-80), but some design work to make it compatible with the Model 4's bank-switching mechanism would be required (eZ80 has no MMU and doesn't re-map RAM in ADL mode in a smaller granularity than 64K, so logic would be required to make it compatible with Model 4-style 32K banks). The eZ80 is available, and not terribly expensive. But it is a fine-pitch surface-mount chip and not really hobbyist-friendly unless you buy one of Zilog's carriers, which are still available. It also has software-scalable clocking, and can be three to five times faster than a Z80 at the same clock rate. So even a 6MHz eZ80 would beat the pants off of a 20MHz Z80 or a 12.5MHz Z280. The eZ80 is available in 50MHz trim, which should be effectively equal to a 200MHz Z80.

The Z8S180 is readily available and hobbyist-friendly. And it is probably the best super-Z80 choice, even today. And there is software, in the form of the XLR8er tools, that can take advantage of the new features and fast local RAM.

Thoughts?
 
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I would be fine with a redesigned version instead of an authentic clone, as long as it functions the same with the supported version.
 
The Z8S180 has the additional advantage of being nearly 100% bus-compatible with the Z80; in my research, I found a hobbyist who did a Z180 CPU for the RC2014 Z80 machine (the simplest Z80 machine you'll find), and there was very little that needed to be done. The only interface I would need is data bus isolation (74HCT245 probably) so that there can be local RAM. With static RAM chips, all you really need is a bit of address decode, with address decode for the bottom 64K of physical RAM to enable the HCT245 for the model 4 bus access. The Model 4 doesn't use DMA, so the data bus buffers could be driven pretty easily.

You could actually do one of these without local RAM and an almost signal-for-signal mapping from the PLCC68 to a DIP40 for the Z80 signals, but part of the advantage is local RAM; with the MMU properly programmed you could map local RAM to shadow the whole 64K of Model 4 RAM. I'm still researching the chips used on the XLR8er and mapping to the known counterparts on the SB180 to see if anything other than a simple buffered direct connection is being done. Out of 22 chips on the XLR8er, one is of course the 64180 itself (U1), but at least 12 are the DRAM array (U6-U13), DRAM mux (U2-U4), and DRAM timing chain (maybe just U16, a 74HC75, although the 5 is really unclear on the diagram, and covered by the cable on Ian's photo). One is an HC138 (U19), likely for address decode, and two are data bus buffers (one probably for the Z80 connector at U21, and one for the DRAM array at U20, but that's speculation). Two are RS-232 level shifters (U22 and U23). This leaves 4 chips: an HCT02 between the 64180 and the Z80 socket at U17, two HC00's (U16 and U19), and an HC74 (U14) which is a flip-flop and could theoretically be part of the DRAM timing chain. Part of this is probably interfacing for the SB-180-compatible expansion bus connector P1.

So we eliminate the DRAM and it's timing chain and mux, and use something like an LT1134 for the level shifter for both serial ports, and we have a much smaller part count (for 512K SRAM: one RAM chip, address decode, data bus buffer: 3 chips; Z80 bus buffer, maybe some glue logic; add another 512K SRAM for 1MB) and it shouldn't be too hard to build. It might be simple enough to do with a simple 2-layer board, but it may be best to just prepare for a 4-layer design, which really isn't that much harder to do and really improves the ground plane and Vcc distribution. The P112 with all parts is only $112, and it has twice as many parts and is a more complex board. The Z8S180 has some built-in abilities to do wait states and clock multipliers; this would require some experimenting to find the limits, but I don't see why 8MHz isn't easily doable, with up to 16MHz probably at least possible, using the max number of wait states. I need to get more information about the wait state generator in the Z8S180 and if it's programmable by address range like the Z280's is (the Z280 allows up to four wait states to be programmed for the lower 8MB of address space independently from the upper 8MB of address space).

More to come.
 
lowen said:
The Z8S180 has the additional advantage of being nearly 100% bus-compatible with the Z80; in my research, I found a hobbyist who did a Z180 CPU for the RC2014 Z80 machine (the simplest Z80 machine you'll find), and there was very little that needed to be done. The only interface I would need is data bus isolation (74HCT245 probably) so that there can be local RAM. With static RAM chips, all you really need is a bit of address decode, with address decode for the bottom 64K of physical RAM to enable the HCT245 for the model 4 bus access. The Model 4 doesn't use DMA, so the data bus buffers could be driven pretty easily.

You could actually do one of these without local RAM and an almost signal-for-signal mapping from the PLCC68 to a DIP40 for the Z80 signals, but part of the advantage is local RAM; with the MMU properly programmed you could map local RAM to shadow the whole 64K of Model 4 RAM. I'm still researching the chips used on the XLR8er and mapping to the known counterparts on the SB180 to see if anything other than a simple buffered direct connection is being done. Out of 22 chips on the XLR8er, one is of course the 64180 itself (U1), but at least 12 are the DRAM array (U6-U13), DRAM mux (U2-U4), and DRAM timing chain (maybe just U16, a 74HC75, although the 5 is really unclear on the diagram, and covered by the cable on Ian's photo). One is an HC138 (U19), likely for address decode, and two are data bus buffers (one probably for the Z80 connector at U21, and one for the DRAM array at U20, but that's speculation). Two are RS-232 level shifters (U22 and U23). This leaves 4 chips: an HCT02 between the 64180 and the Z80 socket at U17, two HC00's (U16 and U19), and an HC74 (U14) which is a flip-flop and could theoretically be part of the DRAM timing chain. Part of this is probably interfacing for the SB-180-compatible expansion bus connector P1.

So we eliminate the DRAM and it's timing chain and mux, and use something like an LT1134 for the level shifter for both serial ports, and we have a much smaller part count (for 512K SRAM: one RAM chip, address decode, data bus buffer: 3 chips; Z80 bus buffer, maybe some glue logic; add another 512K SRAM for 1MB) and it shouldn't be too hard to build. It might be simple enough to do with a simple 2-layer board, but it may be best to just prepare for a 4-layer design, which really isn't that much harder to do and really improves the ground plane and Vcc distribution. The P112 with all parts is only $112, and it has twice as many parts and is a more complex board. The Z8S180 has some built-in abilities to do wait states and clock multipliers; this would require some experimenting to find the limits, but I don't see why 8MHz isn't easily doable, with up to 16MHz probably at least possible, using the max number of wait states. I need to get more information about the wait state generator in the Z8S180 and if it's programmable by address range like the Z280's is (the Z280 allows up to four wait states to be programmed for the lower 8MB of address space independently from the upper 8MB of address space).

More to come.
Click to expand...

Have you done any more on this?

PJH
 
Ok, reviving this thread, rather than reposting much of the same information all over again.

There are a couple of corrections to the first post:
1.) Z380's are still available new from Mouser and others, but they still have substantial disadvantages, including being surface-mount only packages.
2.) Later Z280's aren't as buggy as I originally thought (two real bugs that are pretty serious), and they have been overclocked successfully to 16MHz; but the Z280 is still not a drop-in upgrade for an unpatched TRS-80 DOS. The OUTJMP bug is likely why the Anitek TRX-280 never entered production, but the EX AF,AF' bug, which is far more serious, also has to be addressed. The DMA bugs wouldn't have affected the TRS-80 III/4 DOSes.

Otherwise, I'm still looking for a loaner XLR8er for comparisons, and I'm still trying to find the time to get it done. This past year has been a whole lot more intrusive than I would have liked..... and as a result I have had very little free time. 2018 is slowly calming down a bit, and so an XLR8er workalike might happen. Tibs mentioned a file he has on a floppy somewhere, with ASCII art, of a reverse-engineer of the XLR8er, and I would love to see that file as I'm working on this, since I don't have an XLR8er physically in-hand to look at and compare with.

I am actually looking at a couple of different XLR8er-ish projects here:

1.) The XLR8er workalike/superset, with a Z8S180/33 and 512K static RAM on board, initially clocked and wait-stated identically to the XLR8er (6.144MHz clock; I'll have to look up the default number of wait states), and later with dynamic clocking up to 33MHz for local accesses (local RAM or machine cycles without a bus cycle; only bus cycles that access the TRS-80 hardware would 'downshift' to 6.144MHz or other speed, and with the Z8S180 being a fully static design a dynamic clock should be OK; there is an Atari ST upgrade board that does something like this (see The LaST Upgrade page ) and this design gave me the idea). The workalike design with a straight 6.144MHz clock is the easier of the two, but the superset is the one that I'd like to actually build eventually. This board would have utility in other Z80 systems, too. I would probably not have this as a kit, and would probably use surface-mount parts to make it low-profile so that it could fit in a 4P, which is really tight on space.

2.) TReZ-80, that is, an upgrade using the Zilog eZ80F91 modules. Here there is an additional wrinkle, that of the interface between the 3.3V eZ80 and the 5V TRS-80. But the eZ80F91 modules have local RAM (I'm looking at the one with 512K) as well as local flash and ethernet. I have two of the EZ80F917150MODG boards (eZ80F91 at 50MHz, 512K RAM, 8MB flash, ethernet, 32Mb/4MB serial flash) and they are still available new from Mouser, Digikey, and others for about $80. This module has 0.1 inch standard-spacing headers and thus would be relatively easy to connect to a level shifter/wait-state generator/bus signal stretcher board that would connect to the Z80 socket. The eZ80F91 chip has 256K on-chip flash, and that's the first boot memory, so a simple bootloader/setup program would be loaded there that would set up the proper chip options to allow direct interface to the TRS-80 DOSes. It's at least a thought.....

Thoughts?
 
As I've said before, my main aim would be the first part of 1). i.e. the workalike. The dynamic clocking sounds fun, but for me it would be a bonus rather than a necessity.


PJH
 
Which is more compatible with the base Z80 architecture (including the undocumented instructions)?

The Z380 is listed as having a substantial disadvantage as it's surface-mount only, but for option 1 if you are going to use a surface mount Z180 family CPU then maybe the Z380 is the way to go.
 
The Z180 doesn't support many of the undocumented Z80 opcodes, such as the upper byte and lower byte IX and IY manipulations.

The Z280 actually supports as documented instructions most, but not all, of the undocumented Z80 opcodes.

As to the Z380, it's a finer-pitch quad flat pack instead of the coarser pitch PLCC of the Z8S180. I have a couple of Z380's mounted on adapter boards, but haven't done anything with them since I soldered them to those boards. Perhaps it was a bit of hyperbole to use the word 'substantial' there.....

With the Z180 at least I would have the option of through hole construction with a PLCC68 socket, just like with the CPU280 and its Z280 in a socket.

Other than the lack of those undocumented opcodes the Z180 is the most compatible, as the XLR8er itself proved.
 
Then the Z180 is probably the way to go.

Does anyone know of any commercial software for the I/III/4 that used the undocumented opcodes?
 
Have an XLR8er on one of my 4Ps and have only had problems with Trsdos 1.3 and some versions of Multidos.
May be others.
 
I'm not familiar with this board and know very little about the eZ80. But just as a point of info the Hitachi HD64180 is an easy CPU upgrade requiring only minimal timing adjustments. I used one in my Model II and later Model 16 (many years ago) via a daughter-board plugging into the Z80A socket. I did the hardware mod and Frank did the BIOS change, which was pretty minimal. It was roughly 30% faster on the Model II. I never looked at putting it into a Mod III or IV.

The board was wire-wrapped and mainly just to change the PLCC HD64180 to DIP, though there was a Model II delay line or two there to adjust some timing. Not exactly elegant, but it worked OK. Doesn't sound nearly as fast as the eZ80.

It was a couple of afternoons project between other things and I had a sample Hitachi part I wanted to use...

FYI, for what it's worth...
 
shank said:
I'm not familiar with this board and know very little about the eZ80. But just as a point of info the Hitachi HD64180 is an easy CPU upgrade requiring only minimal timing adjustments. I used one in my Model II and later Model 16 (many years ago) via a daughter-board plugging into the Z80A socket. I did the hardware mod and Frank did the BIOS change, which was pretty minimal. It was roughly 30% faster on the Model II. I never looked at putting it into a Mod III or IV.

The board was wire-wrapped and mainly just to change the PLCC HD64180 to DIP, though there was a Model II delay line or two there to adjust some timing. Not exactly elegant, but it worked OK. Doesn't sound nearly as fast as the eZ80.

It was a couple of afternoons project between other things and I had a sample Hitachi part I wanted to use...

FYI, for what it's worth...
Click to expand...

This sounds pretty interesting. Do you still have the details on the changes?
 
Alphasite said:
This sounds pretty interesting. Do you still have the details on the changes?
Click to expand...

somewhere... i'll cast around for it. i still have the board and should have the bios rom, but not the code changes. it wouldn't be difficult for someone to reproduce. comparing the z80a and hd64180 timing diagrams shows clearly what needs to be changed. for the bios, i think all that needs to happen is to initialize the cpu into a z80 compatible mode. there are some extra instructions and registers available, as well. if i remember correctly, i just went to a parts drawer, plucked out a delay line, installed it, and used a scope to find the tap close enough to work. i pulled clocks off of the CPU board with clips and rg174 coax.
 
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