• Please review our updated Terms and Rules here

Exidy Sorcerer Floppy Disk Controller (Dreamdisk) Replica PCB

johnhalk

Member
Joined
Sep 11, 2023
Messages
26
We have successfully designed, built and tested a replica of the Sorcerer Dreamdisk FDC here in Australia. It based around a WD2793 FDC chip.
It booted successfully from a Gotek using an 80 Track DS/DD 720K .DSK Image.

The DreamBIOS CPM 2.2 uses ZCPR 1.6 CCP and is a very flexible CP/M as it can read over 100 CP/M formats including native dreamdisk, Osborne, Kaypro, TRS-80, Exidy 77 Track soft sector etc.


For your Sorcerer (48K RAM required) MK1 or MK2 - You need to install 2 x 2716 EPROMS with SCUAMONv3.4 monitor which has the Dreamdisk FDC cold boot support.
Replacing the factory Exidy monitor masked PROMS with EPROMS - You can just lift PIN 21 on the 2716 and jumper to PIN 24 (+5v).
You can also cut a trace and add a jumper on the sorcerer PCB if you prefer to plug the 2716 eproms directly into the IC sockets without the kludge above.

Also most Sorcerer's (MK1/MK2) have a factory fault on the PCB where PIN 6 (NMI signal) on the 50 way bus edge connector is not connected internally as there is a small 1mm pcb track missing. You need to remove the Sorcerer PCB and solder bridge a small link to an adjacent PAD to connect PIN 6 to the Sorcerer circuitry.

Apart from the above the rest is mostly plug and play.

Still not sure if these will be available as fully supplied kits (All parts, pcb, inc. eproms) or fully built. This will take some time to sort out.

Regards,
John
Melbourne Australia
 

Attachments

  • image0.jpeg
    image0.jpeg
    154.6 KB · Views: 43
  • image1.jpeg
    image1.jpeg
    118.7 KB · Views: 38
Last edited:
That’s correct. There is the write pre compensation setting which is only needed for 8” disks so not required to be set (WD test pad).

The data separator pulse duration (TG43 test pad) and VCO Frequency (DIRC test pad) need to be set with an oscilloscope.

Something like a PC based Hantek should be sufficient.

John
 
We are also looking at possibly adding HDD decode logic (Ports 50-5F) to add a WD1005 style HDD interface for the Sorcerer.
 
Hi, why do you need this: "SCUAMONv3.4 monitor, which has the Dreamdisk FDC cold boot support." I prefer to have the standard van Montfort monitor ROMs/eproms which was standard in the Netherlands. I think it is possible to put the cold boot address in there as well. What is the cold boot address?
 
Hi, why do you need this: "SCUAMONv3.4 monitor, which has the Dreamdisk FDC cold boot support." I prefer to have the standard van Montfort monitor ROMs/eproms which was standard in the Netherlands. I think it is possible to put the cold boot address in there as well. What is the cold boot address?

Hello, Dreamdisk FDC CP/M will only work with the low level boot code that’s part of Scuamon.
Scuamon is the “Sorcerer computer users of Australia monitor”.
It’s a very powerful monitor and has a lot of enhanced functionality.
There is also a Scuamon80 for 80 Column support if you have a scuamon 80 column video board.

More info on scuamon64 here:

 
Of course the source code should be somewhere but I haven’t seen it yet. I would love to have it.
And certainly it could be added to the monitor 1.3. If I remember correctly it should be version 1.3B for soft sectored floppies. Version C is hard sectored.
 
I have the 1.3/B version in my Sorcerer (now I've the ScuaMon due the Dreamdisk I built) and some time ago I was trying to disassemble it and generate the listing...maybe it's time to finish this project
 

This would be a good project to get working on the Sorcerer which would require some Z80 CP/M coding to get working under Dreamdisk CP/M BIOS.

The z80 interface pcb (UIDE-8) and z80 shim pcb looks plug and play with the sorcerer.

There is some existing code examples that could be used for the Sorcerer Dreamdisk cp/m patching.

Prebuilt boards and shims available here:


I am sure the author could provide some level of guidance on how to approach’s the z80 cp/m drivers.
 
Last edited:
I've been disassembling the scuamon3.4 with dreamdisk boot, and it's got some very interesting code.
my goal is to get commented monitor source code that can be assembled.

the dreamdisk controller has logic that pulls NMI low whenever the Z80 executes a halt instruction and the FDC asserts DRQ or INTRQ.
this is used in the boot code to fake a DMA kind of thing where the NMI vector runs an unconditional INI instruction to the data buffer.

this is faster than testing the DRQ bit and looping, then pulling the data in, incrementing pointer, decrementing count and looping

pretty clever. the boot rom just runs halt instructions inside a loop.
 
That is very interesting - great work !
AFAIK there is the non Dreamdisk FDC version of scuamon v3.4 and also scuamon v3.4 has a 64 column version (standard sorcerer) and a 80 column version (for the 80 column scua video board).

We have also recently started an Exidy Sorcerer Discord server which you can join at:


There is also another Australian developed (back in mid 80s) Digitrio FDC for the sorcerer that plugs directly into the z80 expansion bus and has DMA I/O capability for the disk I/O - Not sure how much faster this would be in real world operation.

John
 
@RedskullDC has done some work on reverse engineering the scuamon monitor.

I have been informed by @exidyboy that originally it was not compiled from source but rather hacks in the object code of the Exidy Monitor but very late in the timeline in a newsletter from the day - there was an article mention that they did manage to
create source code listing for scuamon - but it has never been seen.
 
Hi John, et al.

Here is the disk boot code from SCUAMON 3.4 Dreamdisk edition:

Checks for a disk controller.
If found, restores to track ZERO, Sector #1
(Will try to boot from two drives.)
Sets up an INI instruction at the NMI/HALT Vector at $0066.
Reads 128 byte sector to $0080.
Does *NOT* perform any CRC/LOST DATA checks.


Code:
ROM:EEC1
ROM:EEC1                Check_Port48:                           ; CODE XREF: ROM:E3C8↑p
ROM:EEC1 3E 1E                          ld      a, 1Eh
ROM:EEC3 D3 48                          out     (48h), a
ROM:EEC5 DB 48                          in      a, (48h)
ROM:EEC7 E6 7F                          and     7Fh
ROM:EEC9 FE 1E                          cp      1Eh
ROM:EECB CC CF EE                       call    z, BOOT_SECTOR
ROM:EECE C9                             ret
ROM:EECE                ; End of function Check_Port48
ROM:EECE
ROM:EECF                ; ---------------------------------------------------------------------------
ROM:EECF
ROM:EECF                BOOT_SECTOR:                            ; CODE XREF: Check_Port48+A↑p
ROM:EECF 3E 09                          ld      a, 9            ; restore to track #0, 12ms step rate
ROM:EED1                ; START OF FUNCTION CHUNK FOR WRITE_44_DELAY
ROM:EED1 CD 15 EF                       call    WRITE_44_DELAY
ROM:EED4 CD 0A EF                       call    READ_FDC_STATUS ; wait for Drive ready and command to complete
ROM:EED7 3E 01                          ld      a, 1            ; Sector #1
ROM:EED7                ; END OF FUNCTION CHUNK FOR WRITE_44_DELAY
ROM:EED9 D3 46                          out     (46h), a
ROM:EEDB
ROM:EEDB                loc_EEDB:                               ; CODE XREF: WRITE_44_DELAY+29↓j
ROM:EEDB CD E2 EE                       call    SET_HALT_VECTOR ; $ED A2 = INI instruction. Read from port in C, save to HL+
ROM:EEDE 3E DE                          ld      a, 0DEh
ROM:EEE0 D3 48                          out     (48h), a
ROM:EEE2
ROM:EEE2                SET_HALT_VECTOR:                        ; CODE XREF: ROM:loc_EEDB↑p
ROM:EEE2 21 ED A2                       ld      hl, 0A2EDh      ; $ED A2 = INI instruction. Read from port in C, save to HL+
ROM:EEE5 22 66 00                       ld      (unk_66), hl
ROM:EEE8 3E C9                          ld      a, 0C9h         ; RET
ROM:EEEA 32 68 00                       ld      (LINE), a
ROM:EEED 3E 80                          ld      a, 80h
ROM:EEEF F3                             di
ROM:EEF0 CD 15 EF                       call    WRITE_44_DELAY
ROM:EEF3 21 80 00                       ld      hl, 80h         ; read bytes to $0080
ROM:EEF6 01 47 80                       ld      bc, 8047h       ; read $80 bytes from port $47 (INI instruction above).
ROM:EEF9
ROM:EEF9                READ_SECTOR:                            ; CODE XREF: ROM:EEFD↓j
ROM:EEF9 76                             halt                    ; continue reading sector data until finished.
ROM:EEFA 76                             halt
ROM:EEFB 76                             halt
ROM:EEFC 76                             halt
ROM:EEFD C2 F9 EE                       jp      nz, READ_SECTOR ; continue reading sector data until finished.
ROM:EF00 CD 0A EF                       call    READ_FDC_STATUS ; wait for Drive ready and command to complete
ROM:EF03 FB                             ei
ROM:EF04 E6 18                          and     18h
ROM:EF06 CA 80 00                       jp      z, unk_80       ; jump to loaded sector
ROM:EF09 C9                             ret

Cheers,
Leslie
 
Hi John, et al.

Here is the disk boot code from SCUAMON 3.4 Dreamdisk edition:

Checks for a disk controller.
If found, restores to track ZERO, Sector #1
(Will try to boot from two drives.)

Can you expand on how it is checking for a disk controller and how it chooses which drive to boot from?
 
Back
Top