With the recent relaxation of limits on pictures here I can now post a diagram of my control memory logic map.
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The main components shown consist of 24 six inch square circuit boards containing the very simple Honeywell ICs from the 1960s. The original control memory was a high speed differential mode magnetic core memory with a reputation for being sensitive to the ambient temperature, so for practical reasons I have designed an equivalent using 240 flip-flop ICs. These are mounted on sixteen PCM01 PCBs of my own design, each of which can hold sixteen together with a few output handling ICs. Each PCB is configured as four bits of four registers to reduce the number of I/O lines needed as the PCBs only have 36 pin edge connectors to the backplane.
The fifteen bit input register, which is equivalent to the Z register described in the Honeywell
Series 200 Logic Training Manual, is contained in three PCM03 PCBs, which also contain the high speed twelve/fifteen bit increment/decrement logic and input selectors which can choose either twelve or fifteen bits from the main memory address register, i.e. the S register in the Honeywell manual, or the contents of the main memory data register, the N register in the Honeywell manual, and route them to one of the two and a half characters stored in the input register. Pin and space limitations on the PCBs made the design of the PCM03 boards very tricky and they actually each contain a two bit and three bit register working separately to fulfil all the requirements. The PCBs for these have now been manufactured by my friendly PCB manufacturing company but I haven't assembled them yet.
The fifteen bit output register, which equates to the output buffer of the original core memory, is contained in five three bit PCM02 PCBs, which I created by modifying standard Honeywell flip-flop logic boards. These boards can only handle three bits each because they have to collate eight data channels from the PCM01 boards and this task alone requires 24 of the 36 connector pins. The PCM01 boards themselves first route the sixteen register outputs onto eight channels to reduce the number of output pins needed on them. Only one register is accessed in any clock cycle of course. The PCM01 boards can also read in the contents of the output register so that the contents of one register can be copied to another, although I have also included a limited ability to do some copying directly inside the PCM01 boards, something that wasn't possible using a core memory. As flip-flops aren't read destructively like magnetic core memory the actual cycle of operation of my memory is different from the original and this should reduce timing restrictions.
The diagram differs from the layout in the Honeywell manual because data going from the N register to the Z register actually flows through the arithmetic logic unit there to cater for address indexing, but I will add this function later and there wasn't room on my diagram to show it anyway. Address indexing was actually one of the optional features in the original 201 processor and I am only initially attempting to reconstruct the basic machine without any options. The machine that I worked on in the 1960s didn't have this feature, so I am quite used to programming the H200 without it, as my demonstration programme to calculate Pi on my website proves.
While my IC based control memory is internally quite different from the original core memory it fits into the original architecture and allows that to be reproduced in my machine. My pragmatic approach is similar to that employed by the auspicious British
Computer Conservation Society in their
EDSAC replica project, where they are using wire delay line memories in place of the original mercury delay lines, which were serious beasts to maintain, so I think that I am in good company in doing it. In contrast the main memory of my machine is almost identical to the original with only some small changes to the backplane wiring to build a more compact 8k memory in place of the original 16k module. The main memory uses original core memories and unmodified Honeywell logic boards plus a few closely copied replicas to make up the numbers as I didn't have a full set.