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How did computers in the '70s avoid frying DRAM chips?

stepleton

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I think this is a fairly basic electronics question.

If you read datasheets for old DRAMs that used multiple power supplies, you'll find warnings like these:

mos_dram-1979_Motorola_Memory_Data_Book-p2-61.png

That's "Forward biasing this supply (that's Vbb) with respect to Vss will destroy the memory device". You'll also find instructions like the last line here:

mos_dram-1979_Motorola_Memory_Data_Book-p2-17.png

"Vbb must be applied prior to Vcc and Vdd. Vbb must also be the last power supply switched off."

Mostek at least did you the courtesy of explaining the reason for this (although surely many readers of the datasheet would have known it anyway), and they also gave you perhaps a bit more leeway with some of their devices:

mos_dram-1979_Mostek_Memory_Data_Book_and_Designers_Guide_Mar79-p108.png

"The Vbb supply is an extremely important 'protective voltage' since it performs two essential functions within the device. It establishes proper junction isolation and sets field-effect thresholds, both thin field and thick field." Plus more about how you can leave Vbb at 0V for around five seconds.

My question is: what kinds of techniques did system designers use to make sure that they were ready with the reverse bias voltage before the other rails came up? I'm thinking in particular of S100 cards like this one:

http://www.s100computers.com/Hardware Folder/Dynabyte/16K DRAM/16K DRAM.htm

where it looks like you just have a bunch of voltage regulators and not a whole lot of machinery there dedicated to power supply power-up sequencing, at least that I can find. (Was there any?) Did you find other precautions, like fitting a nominally reverse-biased diode so that Vbb could never exceed Vdd?
 
Generally, they didn't bother in my experience, which goes back only to the TMS4030 (pretty much a clone of the Intel 2107).
 
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On the Nascom PSU (a British Z80 kit computer), diodes were fitted to the output of the regulators that would conduct if the voltage rails attempted to “come up” “out of sync” with each other.

This would limit the maximum “reverse voltage” potential to that of the forward voltage drop of the diode at the expense of “dumping” the current to the lower voltage rail (generally 0V/GND). However, a diode was also fitted between +5V and +12V rails for the same reason.

Dave
 
Thanks Dave. I can see what you mean in this schematic from http://www.nascomhomepage.com/pdf/3a.PDF:
nascom.png
So it looks like a nice chain of reverse-biased diodes: we have

(-12V) ----D10->|---- (-5V) ----D7->|---- (0V) ----D3->|---- (+5V) ----D5->|---- (+12V)

Nice of them to add indicator LEDs on every rail as well!
 
That’s the beastie.

Yes, the LED indicators were a nice touch - but the 3A PSU was a bit low for a significantly expanded system.

The diodes were a very simple solution...

Dave
 
My AES/Lanier has a big linear supply which has a few diodes and resistors in the regulation side of the circuit that force the supply to bring the rails up in order.

What it does not have is a way to shut down the supply if one rail fails. It will crowbar if the rails go out of spec upwards in voltage though.

​​​​​ Phil
 
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