While the Superbrain is a bit different from what I'm going to describe to you, you can use the code I'm going to mention as a template of sorts of what a WD1000-compatible bootloader would look like.
First, the TRS-80 model 4p has code to boot from WD1000; see
http://fjkraan.home.xs4all.nl/comp/trs80-4p/bootRom.asm for a commented disassembly of the 4P boot ROM. The disk I/O routines start at location 08B5H. On the TRS-80 4P, the WD1000 registers start at port C8H (C0H-C7H are for other hardware on the TRS-80-specific boards) and run through CFH, so look through this code for OUT's to those ports and IN's from those ports. The 4P is an interrupt mode 1 machine, and this is how disk I/O is done on such a machine.
Likewise, the TRS-80 Models 2 and 12 use the WD1000; see
http://fjkraan.home.xs4all.nl/comp/trs80m2/trs80m2boot.zip for a zip file of a commented boot ROM 're-engineering' by Eric Smith for the M2 and M12, in several versions. The TRS-80 Models 2, 12, 16, 16B, and Tandy 6000 are interrupt mode 2 machines with the typical Z80 chipset of Z80DMA, Z80PIO, and Z80CTC chips, so this will give you an example of HDC I/O in an IM2 setting.
While none of this is Superbrain-specific, it should give you a couple of good examples of how a Z80 machine (capable of booting CP/M, incidentally, as well as the Tandy-proprietary TRSDOS and the LSI/Misosys LS-DOS operating systems) programs and uses a WD1002-05 (or in the case of the Tandys, the WD1000-TB1) for booting.
