2 is impossible. It would require some flash ram or eeprom chip added to the design.
For 1: in the Quartus II code there is a module callled ctrl_params.vhd there is a
peak: integer range 0 to 128*1024*1024 := 0;
make it to 256*1024*1024 in both lines (it sets the value after)
3: once you find the parameters you can edit the schematic.bdf for each CGA,EGA,MDA and HGC you can set the properties in the box that contains values for: c_phase, c_samples, c_top_border (vpos) and c_left_border (hpos). Again you change in the .BDF file (instance) not in the ctrl_params.vhd, the values there are there only for the time you instance it. Hpos and Vpos are reversed: 0 means all to the right/down and forward. Good luck and have fun. And a very fast multicore computer to compile the FPGA code...