RichCini
Veteran Member
Since I have the Color Magic reproduction working, I was going to tackle the Thunder 186. This is an 80186-based all-in-one card with a floppy controller and 256k of DRAM. There are only two PALs on it, and they seem to be simple address/status decoders, so I figure they will be easier to reverse.
I spent some time drawing the schematics (originals attached) and there’s something I need some help with. Like the ColorMagic, Lomas used stacking memory sockets, in this case allowing for 36 DRAM chips (4164-15L, total of 256k of parity RAM) in the space of 18. They are arranged in even/odd rows using one CAS for all and two RAS signals from the TMS4500/VL4500 DRAM refresh controller for the lower and upper chips in the socket. The TMS4500 tops-out at 64K devices, but the board has a DIP-48 footprint which allows the alternate controller, the VL4501, to be mounted. The VL4501 can handle 256K devices. The TMS4500 is bottom-justified in the socket so the signals line-up.
Given the board density and the lack of stacking sockets, I need to convert this to something that could use only one or two rows of unstacked chips.
The manual makes no mention of the alternative DRAM controller, with the only reference being in the schematics. I’m thinking that if I switch to the VL4501 and use only 18 41256-15L chips (256kx1) it might work. But, that’s what I wanted to ask the group about. The memory schematics are on page 3 of the attached. I guess I could make a mezzanine board with 36 chips, but I'd like to avoid that -- I'd need 32 pins (2x8 pin header times 2), but that might make routing the main board easier. I know several PC/ISA memory expansion boards did that, like the 4MB memory board in my Compaq DeskPro/386.
I understand that AST Research used the VL4501 in their PCjr sidecar memory, but I can’t find a manual or schematic of it.
If anyone has suggestions, I'm all ears. Thanks!
Rich
I spent some time drawing the schematics (originals attached) and there’s something I need some help with. Like the ColorMagic, Lomas used stacking memory sockets, in this case allowing for 36 DRAM chips (4164-15L, total of 256k of parity RAM) in the space of 18. They are arranged in even/odd rows using one CAS for all and two RAS signals from the TMS4500/VL4500 DRAM refresh controller for the lower and upper chips in the socket. The TMS4500 tops-out at 64K devices, but the board has a DIP-48 footprint which allows the alternate controller, the VL4501, to be mounted. The VL4501 can handle 256K devices. The TMS4500 is bottom-justified in the socket so the signals line-up.
Given the board density and the lack of stacking sockets, I need to convert this to something that could use only one or two rows of unstacked chips.
The manual makes no mention of the alternative DRAM controller, with the only reference being in the schematics. I’m thinking that if I switch to the VL4501 and use only 18 41256-15L chips (256kx1) it might work. But, that’s what I wanted to ask the group about. The memory schematics are on page 3 of the attached. I guess I could make a mezzanine board with 36 chips, but I'd like to avoid that -- I'd need 32 pins (2x8 pin header times 2), but that might make routing the main board easier. I know several PC/ISA memory expansion boards did that, like the 4MB memory board in my Compaq DeskPro/386.
I understand that AST Research used the VL4501 in their PCjr sidecar memory, but I can’t find a manual or schematic of it.
If anyone has suggestions, I'm all ears. Thanks!
Rich