%
% SP-MPE
%
% 10M winchester, 2*1M discdrives, 100K ramdisc
% 1*1M discdrive wd1002
% 1*56K user, TMS9902 term, Centronics print
% 870630 Base 05a00 Version 3.0
% Must be used with CONFIG.NORMAL moved to CONFIG.MOD
% - BEFORE WINCHESTER IS INITIALISED USE CONFIG.X -
%
% Configuration parameter section
%
nprior equ 10 highest process priority
nusers equ 1 number of users on system
nintlv equ 5 number of interrupt levels used
nproc equ 1 max number of processes per user
bsize equ 01000 system buffer pool size
dtbufl equ 256 data transfer buffer length
ticksc equ 40 clock ticks per second
slice equ 13 clock ticks per user time slice
psynct equ 60 periodic SYNC$ time in seconds
trmobuf equ 3 maximum output msgs backed up to term
trmibuf equ 3 maximum input msgs backed up to term
maxof equ 10 maximum open files per user
nblocks equ 10 number of file paging buffers
blockbsz equ 256 largest block size used (by any SU)
nmemi equ 10 number of memory Inodes
maxpar equ 10 maximum program parameters
scrmax equ 3 maximum SCRIPT$ file nesting
%
% Configuration table section
%
. * Terminal pointers go here
data trm1
. * end
. * Storage unit pointers go here
data su1
data su2
data su3
data su4
data su5
. * end
. * Memory bank pointers go here
data mb1
data mb2
data mb3
. * end
. * Terminal control tables go here
trm1 data trm902,trm1d,trm1ib,trm1ibe,trm1eb
data trm1ebe,illogin
bss chbss
trm1d data 080 cru software addr.
byte crsb2+crpenb+crlen7 9902 control reg.
byte 01 non int. send, check DTR
data 9600 baud rate
data 0 onboard=0, offboard<>0
trm1ib bss 80
trm1ibe .
trm1eb bss 20
trm1ebe .
. * end
. * Real time clock table goes here
rtct* data rtc995,rtctd
rtctd data 18750 25 ms / interupt
. * end
. * Clock/calendar table goes here
. * end
. * Storage unit tables go here
su1 data 256,1,22,23,500,wdwini,hdskt,1
data 09b80,256,09b80
data 0,0,0
bss 10
bss dinl
su4 data 256,1,2,3,96,wdwini,hdskt,2
data +(16*80*2),256,+(16*80*2)
data 0,0,0
bss dinl
hdskt data 0ff00 device addr
data cbuffh buffer in common
data hrdut unit table
data 2 units on controller
bss 66
hrdut data hrdut1,hrdut2
hrdut1 byte winch0+sec256+eccbit unit select code
byte wsr35u step rate code
data 4 # of heads
data 256 sector length
data 32 sectors / trk
data 311 trks / head
data 0 interlace tbl addr, 0 if none
hrdut2 byte flppy0+sec256 unit select code
byte fsr3m step rate code
data 2 # of heads
data 256 sector length
data 16 sectors / trk
data 80 trks / head
data hlct16 interlace tbl addr, 0 if none
.
su2 data 256,1,1,2,12,tmx909,dsk1t,1
data +(16*80)/2,256,+(16*80)/2
data 0,0,0
bss 10
bss dinl
su3 data 256,1,1,2,12,tmx909,dsk1t,2
data +(16*80)/2,256,+(16*80)/2
data 0,0,0
bss 10
bss dinl
dsk1t data 0f140,001c0,dmabuf,d1ut,2
bss 66
d1ut data d1ut1,d1ut2
d1ut1 byte 000 =1 then test if two sides (8")
byte 000 step rates 0=A, 1=B
byte 000 ()
byte 000 drive size : 0=5" , 1=8"
byte 000 select bits : 00,01,02,03
byte 001 select bits : 01,02,04,08
byte 001 sides : 00=single,01=double
byte 001 density : 00=single,01=double
data 128 single density sector size (bytes)
data 16 sectors/track
data 80 tracks/side
data ilct16 interlace table,0=none,ilct16/26
d1ut2 byte 0,0,0,0,01,02,01,01
data 128,16,80,ilct16
.
stepratea equ 3 time / step in ms
headsetla equ 15 head settling time in ms
headloada equ 50 head load time in ms
steprateb equ 3 time / step in ms
headsetlb equ 15 head settling time in ms
headloadb equ 50 head load time in ms
.
stepra* equ stepratea*2+1
headsa* equ headsetla*2+1
headla* equ headloada*2+1
steprb* equ steprateb*2+1
headsb* equ headsetlb*2+1
headlb* equ headloadb*2+1
.
su5 data 0,0,0,0,30,memfil,memf1t,1
data 0,0,0,0,0,0
bss 10
bss dinl
memf1t data m1ut1,2
m1ut1 data mb2,mb3
. * end
. * User memory bank tables go here
mb1 data 0e000,enmb1,dsmb
mb2 data 0e000,enmb2,dsmb
mb3 data 0a000,enmb3,dsmb
. * end
. * Printer control tables go here
pr1 data prcent,pr1t,0,0,0,0
data 0,0,0,0
data 3,68,3
bss pfbss
pr1t data 0800 CRU address
data 01 on=0 , off<>0 (main board)
. * end
. * Printer offline access tables go here
off1 data pr1,5,128
bss 30
. * end
. * Background batch control tables go here
. * end
. * Special file name tables go here
data 9,xsnsf1,0fe,pr1,spfprt
data 9,xsnsf2,0fd,off1,spfapq
. * end
. * Special file names go here
xsnsf1 text "PRINT.DEV"
xsnsf2 text "PRINT.OFF"
. * end
. * Interrupt routines for level 1 go here
. * end
. * Interrupt routines for level 2 go here
mov r12,r5
li r12,01fda point to MID flag
tb 0 MID ?
jeq midint yes, go and crash system
blwp snap$ no, then it is an Arithmetic Overflow
text "Arithmetic Overflow.&"
even
jmp finint2
midint
blwp snap$
text "\Macro Instruction Detect. Illegal opcode.&"
even
finint2
mov r5,r12
. * end
. * Interrupt routines for level 3 go here
li r2,rtc995
mov rtvint(r2),r1
li r7,rtct
bl *r1
. * end
. * Interrupt routines for level 4 go here
mov r12,r1
clr r12
sbz 1 turn off keyboard
mov r1,r12
.
li r2,trm902
mov cvint(r2),r1
li r7,trm1
bl *r1
.
li r7,pr1
mov pfdrvv(r7),r2
mov cvint(r2),r1
bl *r1
.
li r2,tmx909
mov bvint(r2),r1
li r7,dsk1t
bl *r1
.
li r2,wdwini
mov bvint(r2),r1
li r7,hdskt
bl *r1
. * end
%
% Memory bank control section
%
. * Memory bank enable and disable routines go here
mapper equ 0f100 memory mapper memory mapped addr.
map1start equ 060 upper 8 bits of 20 bit addr.
map2start equ 070
.
sysmap* ckof
rt
sysdmap* rt
.
enmb1*
mov membank1,membankwp+2*r3
blwp enable get some wp of my own
rt
enmb2*
mov membank2,membankwp+2*r3
blwp enable
rt
enmb3*
mov membank3,membankwp+2*r3
blwp enable
rt
.
enable data membankwp,enablepc
enablepc c r0,r3 is the mapper unchanged
jeq setmapon1 y, turn on the mapper
mov r3,r0
li r1,mapper point to reg 0
li r2,16 do all registers
mb1loop
movb *r3+,*r1+ only 8 bits is enough
inc r1 make sure it points to next mreg
dec r2 have we done all mreg
jne mb1loop no one more
setmapon1
ckon let the mapper go !
rtwp
.
dsmb* ckof return to system
rt
.
membank1 data membank1map
membank2 data membank2map
membank3 data membank3map
membankwp data 0000 make r0 something <> membank1,2,3..
bss 30 give r1-r15 someplace
.
. Mapper
. Reg
membank1map
byte 00 reg0 00000-00fff }
byte 01 reg1 01000-01fff }
byte 02 reg2 02000-02fff }
byte 03 reg3 03000-03fff }
byte 04 reg4 04000-04fff }
byte map1start+05 reg5 65000-65fff }
byte map1start+06 reg6 66000-66fff }
byte map1start+07 reg7 67000-67fff } user mem 56K
byte map1start+08 reg8 68000-68fff }
byte map1start+09 reg9 69000-69fff }
byte map1start+0a regA 6a000-6afff }
byte map1start+0b regB 6b000-6bfff }
byte map1start+0c regC 6c000-6cfff }
byte map1start+0d regD 6d000-6dfff }
byte 0e regE 0e000-0efff NOS common mem
byte 0f regF 0f000-0ffff memory mapped I/O
membank2map
byte map2start reg0 70000-70fff }
byte map2start+01 reg1 71000-71fff }
byte map2start+02 reg2 72000-72fff }
byte map2start+03 reg3 73000-73fff }
byte map2start+04 reg4 74000-74fff }
byte map2start+05 reg5 75000-75fff }
byte map2start+06 reg6 76000-76fff }
byte map2start+07 reg7 77000-77fff } ramdisc part 1 56K
byte map2start+08 reg8 78000-78fff }
byte map2start+09 reg9 79000-79fff }
byte map2start+0a regA 7a000-7afff }
byte map2start+0b regB 7b000-7bfff }
byte map2start+0c regC 7c000-7cfff }
byte map2start+0d regD 7d000-7dfff }
byte 0e regE 0e000-0efff NOS common mem
byte 0f regF 0f000-0ffff memory mapped I/O
membank3map
byte 0f reg0 0f000-0ffff } top of internal ram
byte map1start+0e reg1 6e000-61fff }
byte map1start+0f reg2 6f000-62fff }
byte map2start+0e reg3 7e000-7efff }
byte map2start+0f reg4 7f000-7ffff } ramdisc part 2 40K
byte map1start reg5 60000-60fff }
byte map1start+01 reg6 61000-61fff }
byte map1start+02 reg7 62000-62fff }
byte map1start+03 reg8 63000-63fff }
byte map1start+04 reg9 64000-64fff }
byte 0a regA not used
byte 0b regB not used
byte 0c regC not used
byte 0d regD not used
byte 0e regE 0e000-0efff NOS common mem
byte 0f regF 0f000-0ffff memory mapped I/O
. * end
