Question for the GAL Gurus: Most efficient Divide by three?

[Eudimorphodon]

I'm still sort of a newb at this whole "programmable logic" thing, so I have this strong feeling I'm probably missing a really obvious and cool way to accomplish a thing. So here's a question for the wizards: what's the best strategy for implementing non-power-of-2 clock dividers in a GAL?

A project that I'm slowly plugging away on, at least in the back of my head, is an idea for a kind of "retro-recreation" of a TRS-80 Model III computer, and for it it'd be nice if I could derive 4mhz and 2mhz clocks from a master 12mhz pixel clock in the video section. Banging on it for a while this is the best divide-by-three equation I could come up with:

GAL16V8   ; Divide by three test
DIVTHREE  ; 


Clock CL    NC    NC    NC    NC   NC  NC  NC  GND
/OE   A     COUT  NC    NC    NC   NC  Q1  Q0  VCC


Q0.R = /A * /Q0


Q1.R = /A * /Q1 *  Q0
       + /A *  Q1 * /Q0


A = /Q0 * Q1


COUT = A
      + /Q0 * /Q1 * CL

DESCRIPTION

this is a divide-by-three circuit, 50% duty cycle

registered outputs are signed with the postfix .R

Q0 and Q1 are a two bit counter.
A goes high when Qx=2, causing counter reset to 0 on next clock, skipping Qx=3

COUT is high when A is high (Qx = 2) + 1/2 of (Qx=0)

It takes four output registers to implement; two for a 2-bit counter, one for a reset-on-2, and one to stretch the reset another half input cycle to make it a 50% duty cycle. (If I would be happy with a 33/66 duty cycle then I could get rid of COUT and use A directly.)

Is there a better way to do this, or is this good enough for government work?

 

[Eudimorphodon]

Doh. Of course, right after I post I thought of an optimization:

GAL16V8   ; Divide by three test
DIVTHREE  ;


Clock CL    NC    NC    NC    NC   NC  NC  NC  GND
/OE   COUT  NC    NC    NC    NC   NC  Q1  Q0  VCC


Q0.R = /COUT * /Q0


Q1.R = /COUT * /Q1 *  Q0
       + /COUT *  Q1 * /Q0


COUT = /Q0 * Q1
      + /Q0 * /Q1 * CL

It occurred to me that the counters shouldn't care if the "reset" state was only stretched half a clock, as long as it was off before the next rising transition, so I was able to get it down to three output registers.

Still... I guess the questions still stands, is there a better way yet to manage this?

 

[Eudimorphodon]

So... starting from the divide by three I came up with above I hacked together a switchable divide by three/six circuit. Normally I'd think it'd make the most sense to either divide by two and use that as the clock for the divide by three, or vice-versa, but since the GAL has a single input clock I decided to attack the problem by expanding the counter to three bits, resetting it at six (burning a dedicated feedback pin for that), and having it output two one-and-a-half clock cycle highs per six cycles for the /3 mode and one three-cycle high in divide-by-six mode.

Still interested if anyone has a better general-purpose way for doing clock divisions, but, well, here's the scope output that shows this at least works. Divide-by-three:



Divide by six:



(Switchable based on the high/low state of an input pin. This is running at... probably around 500khz?, the input clock is driven by an arduino using the standard "pin" command which is pretty slow. Oscilloscope is dialed to two microseconds per division.)