Reversing PALs for various S100 boards

[RichCini]

Here's the schematic so far. I added a second socket for the 20L10. Need to more fully examine how to handle the data I/O bits as bits are added to the middle between the output-only bits.

https://github.com/RichCini/PALReader

Rich

 

[daver2]

Any chance of PDF'ing it please?

I am currently on my phone (and my work's laptop has github banned).

Dave

 

[RichCini]

You bet! It's blocked at my work, too. I hate that

Rich

 

[daver2]

Cheers,

I have only given it a quick check. I will have to check the PAL socket wiring out tomorrow.

The only suggestion I would have for now would be to tie the unused inputs of the second 8:1 multiplexer either high or low. The unused inputs will be read, so tying them would guarantee that they read as logic '0' or '1'.

Dave

 

[RichCini]

Thanks Dave. All unused inputs tied to ground for now. I have a rough component placement done; should take no time at all to route given the small size, etc.

 

[RichCini]

A few additional notes:

• Looking at the ordering of the pin name array in the reading code, the bits read by the LS151 from the 16L8 might be backwards in the schematic.
• Expanding to the 20L10 may require changing the input lines connected to the resistors from PAI10...PAI15 to PAI12...PAI17.
• Not sure if the bit ordering on the new U6 (for the 20L10) is correct.

I'd really like to confirm at least whether the 16L8 part is correct. Chuck's schematic (palread3) has a series of jumpers to connect to the PAL and I'm trying to make a board out of it with no jumpers which, naturally, does reduce configurability.

Rich