Let's explain a little bit more...
The CPU (if it has a signal on pin 3 - SYNC) is fetching and executing instructions. We don't know where from yet...
The CPU should be outputting the address on the address pins of the CPU (A0 to A15) and the memory mapping register pins (P0 to P3).
With the oscilloscope set to single channel (and triggering on that channel) you should see activity on a subset of (and maybe not all of) A0 to A15 and P0 to P3 ON THE CPU.
You will have to adjust the oscilloscope timebase to see anything - and (even then) (depending upon WHAT the CPU is executing) you may not be able to get a stable oscilloscope trace. This is just life...
The CPU address bus (A0 to A15) is buffered by U19 and U18. In theory, what appears on the CPU address bus (A0 to A15) should appear on the input to (and output from) the address buffers. The address buffer outputs go to the ROM/EPROMs.
Likewise, the CPU P0 to P3 signals are buffered by U58 and then disappear off to more logic.
Now, here is the issue, the address buffers (U19 and U18) are controlled by a signal on pin 19 such that they can be enabled and disabled. So, if they are disabled, the CPU address lines still go TO U19 and U18 - but they may NOT appear on the output side (and hence on the pins of the ROM/EPROMs).
Look at the schematic
https://www.zimmers.net/anonftp/pub/cbm/schematics/computers/b/8256059-01.gif and does this make sense?
Dave