CP/M plus banking question

[alank2]

If CP/M plus has a common area at the top and switches out the lower area, how can it or does it handle interrupts which are in the lower area?

 

[krebizfan]

IIRC, the interrupt area is duplicated in each bank. Gets more complicated with MP/M where some banks don't have to cover the entire memory region below BDOS.

 

[durgadas311]

Yes, interrupts have to be replicated to each bank if using 8080 interrupt modes. If the interrupt vectors might be modified on-the-fly, it gets trickier.

Same is true for MP/M, except it only applies to banks that are based at address 0000. Gets tricky if the system is using RST instructions for some system purpose, or even by an application that might run in a bank not based at 0000 (PRL). Also, all MP/M banks require the standard CP/M Page 0 setup, like the JMPs at +0000 and +0005, and the iobyte etc. I forget how much of the page 0 setup is done by BDOS/XDOS and how much is done by XIOS.

 

[JohnElliott]

The usual way is that the interrupt handler is in the common area and the jump instructions at the bottom of memory are set up the same in all banks.

The Amstrad PCW even gets to use the Z80 NMI (for floppy I/O) -- the vector is set up at 66h at the bottom of bank 0 and banks 2+, and there's a latch that disables it so that it never fires while the TPA is paged.

 

[alank2]

Just out of curiosity, could DR have done it the other way around? Could they have decided to make the top the bank and the bottom the common area?

Can a bank be switched out while code is running in it as long as it is done so that once the switch is done the next instruction is the right one?

 

[daver2]

To answer your last paragraph, potentially yes. This does assume no cache and/or prefetch queue, or anything smart like that.

Also, memory management and the like can play havoc.

You obviously need to thoroughly comment your source code!

Needless to say, this scheme is not too smart. Neither is self-modifying code, but people still do it!

Dave

 

[krebizfan]

I think that swapping using higher regions instead would require duplicating the BDOS on systems that had to swap on 16K boundaries. Would waste a lot more memory.

 

[durgadas311]

Just out of curiosity, could DR have done it the other way around? Could they have decided to make the top the bank and the bottom the common area?

Can a bank be switched out while code is running in it as long as it is done so that once the switch is done the next instruction is the right one?

CP/M (and MP/M) is oriented around the OS residing in high memory, so the only scheme that makes sense is to have common memory up high.

Yes, a program doing it's own banking could switch banks provided it knows that the next PC fetched from has valid code. However, I'm not sure if CP/M 3 will handle that since it expects bank 1 to be the program (TPA). Things like interrupts or BDOS calls might not return to the proper bank or copy data to/from the correct bank. It depends on how pervasively "bank 1" is hardcoded, in both the BDOS and the BIOS.

 

[Svenska]

Could they have decided to make the top the bank and the bottom the common area?

Theoretically yes, practically no. CP/M programs are loaded at 0x0100, which would be in the common area - and the BDOS/BIOS are expected at the top of memory, which is switched out. It would be an inefficient and complex system, and incompatible with existing applications.

Moving programs to a higher address, as was done for some unmodified TRS-80 models, would be possible, but be less flexible overall. So not a practical approach.

Can a bank be switched out while code is running in it as long as it is done so that once the switch is done the next instruction is the right one?

Yes, but it is tricky. You need to replicate the bank switching code in all banks, and make sure to continue execution somewhere. Some NES games can only switch the whole ROM area at once, so they do that. Others use some precious RAM to execute the switching routine from.