Obtainium Retro
Member
- Joined
- Mar 23, 2024
- Messages
- 22
As the master of vaporware, I've successfully not released dozens of Sinclair QL hardware bits and bobs. I think it's time that changed. I've done so much work on so many things, and it's time to just go through the large pile of designs and filter them and condense them down into something useful, manageable and manufacturable. Owning the Sandy designs I have a nice base of reference designs to start from.
A few years ago I reverse engineered the Super Gold Card and retargeted the logic to a later and still available CPLD. I made other changes, like dropping DRAM support and using multiple fast 1Mx16 SRAMs, implementing 4 MB easily, and 8MB with issues. The biggest change was to support faster 68030 devices, up to 40 MHz. This was always a dodgy affair, living on breadboards, crashing often because of the limitations of building it on breadboards, but it was handily more fun than the 25MHz 68020 Super Gold Card. Another design I did disabled DRAM refresh on an existing Gold Card, and added 2MB SRAM to replace the DRAM. This did offer a modest speed boost to the Gold Card for minimal cost.
I made a (since independently developed and better than anything I did) CPLD video chip. There is a separate effort that has borne fruit, but my effort only supported mode 4 or mode 8. The CPLD could be programmed with the equations for a single mode, and you were just stuck with that mode.
I've decided now to bring those two projects together into an FPGA to try to make a complete SGC replacement. Instead of using a SGC-style boot ROM to import and edit existing ROMs I think I'll use a custom Minerva install designed to boot in a way that fully supports future native booting into Minerva or SMSQ/E.
I've spouted a bunch of nonsense over the years and only ever released the most basic things I had confidence in. It's time to man up and do something meaningful.
I'll post progress pics here as time goes by. This is a place marker. I won't be discussing it on the QL Forum or discord. I think this is the right place...
Target is:
68020 or 030 at 25, 33 or 40 MHz
4M of RAM minimum
DD/HD floppy interface
parallel port
dual fast serial
PS/2 keyboard/mouse
A few years ago I reverse engineered the Super Gold Card and retargeted the logic to a later and still available CPLD. I made other changes, like dropping DRAM support and using multiple fast 1Mx16 SRAMs, implementing 4 MB easily, and 8MB with issues. The biggest change was to support faster 68030 devices, up to 40 MHz. This was always a dodgy affair, living on breadboards, crashing often because of the limitations of building it on breadboards, but it was handily more fun than the 25MHz 68020 Super Gold Card. Another design I did disabled DRAM refresh on an existing Gold Card, and added 2MB SRAM to replace the DRAM. This did offer a modest speed boost to the Gold Card for minimal cost.
I made a (since independently developed and better than anything I did) CPLD video chip. There is a separate effort that has borne fruit, but my effort only supported mode 4 or mode 8. The CPLD could be programmed with the equations for a single mode, and you were just stuck with that mode.
I've decided now to bring those two projects together into an FPGA to try to make a complete SGC replacement. Instead of using a SGC-style boot ROM to import and edit existing ROMs I think I'll use a custom Minerva install designed to boot in a way that fully supports future native booting into Minerva or SMSQ/E.
I've spouted a bunch of nonsense over the years and only ever released the most basic things I had confidence in. It's time to man up and do something meaningful.
I'll post progress pics here as time goes by. This is a place marker. I won't be discussing it on the QL Forum or discord. I think this is the right place...
Target is:
68020 or 030 at 25, 33 or 40 MHz
4M of RAM minimum
DD/HD floppy interface
parallel port
dual fast serial
PS/2 keyboard/mouse