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Ideas for a "switchable" 8-bit ISA Riser.

Eudimorphodon

Eudimorphodon

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Recently I did some hacking on my Tandy 1000 HX test mule to figure out strategies for freeing up the parts of the memory map occupied by the mostly useless onboard DOS and Deskmate resources so they could be used for expansion memory and peripherals. The mission was mostly successful, and in part to demonstrate that everything works (and in other part because my Commodore 1084 monitors are succumbing to senility-related diseases) I've been running a VGA card in the Tandy "Plus Bus" riser on my combo expansion board since then:

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it's been working well, but having the VGA card *does* make the machine incompatible with a significant body of Tandy 1000/PCjr software so I've been wondering if it might be possible to make a "switching" riser that would allow me to disable whatever card is plugged into it with a simple toggle switch. My question is thus: what lines do I need to "switch off" to make this happen?

The first idea I was to use three 74LS244 buffers to completely buffer the address lines A0-A19, with pull-up resistors so when the riser is switched "off" the only address the card will ever see is FFFFFh. I don't think it's likely there will be any ISA cards that decode that area, so... would there be any other lines that would need to be switched for this to work? I would hope most cards would just sit there quietly and never assert themselves on the data bus under these circumstances, but are there cards that might rudely try pulling down other lines if not initialized?

(Also, it's safe to assume that any "normal" ISA card will only read the address lines and not try to assert them? I found one reference that claimed that ISA address bus masters were "possible" but that's going to be a rare exception?)

Alternatively, I was wondering if it *might* be sufficient to simply put a buffer in front of the MEMR/MEMW and IOR/IOW lines, so the plugged in card would never see anything but a "1" on those signals? This would not prevent the chip enable circuitry on the cards from decoding their peripheral addresses... but I'm not sure if that would be an issue or not? The one thing I can kind of imagine is if the card in question has a buffer like a 74LS245 on it that's set up so a "1" on its "DIR" signal sets it for "towards the bus", in which case it might load the bus with whatever it's getting from its "private" side? That shouldn't matter if there's no actual clash between the "hidden" peripheral and what remains active, but I'm worried about the edge case that might exist if, say, a buffer on a video card asserts "nothing" on the bus when onboard video is accessed?

Anyway, curious if anyone's ever built anything like this before.
 
Buffer and gate off the RD/WR (memory and I/O) strobes. Nothing will ever drive the bus unless those go active.

There isn't a master request signal on 8-bit ISA. That was 16-bit only. There is a bus request signal on the Tandy 8-bit ISA implementation for non-DMA machines (A, EX, HX, ..) but AFAIK that is only used by the 8237A memory expansion cards.
 
eeguru said:
Buffer and gate off the RD/WR (memory and I/O) strobes. Nothing will ever drive the bus unless those go active..
Click to expand...

What about the case of a 74LS245 buffer that's activated by the same chip select line as the peripheral(s) it's buffering? For instance, how the 245 is activated on the Low Tech memory board:

https://www.lo-tech.co.uk/wiki/File:Lo-tech-1MB-RAM-Board-schematic-r02.png

Doesn't this device assert on the "out" side of itself whatever it sees on the "in" side whenever CE is asserted? So in the hypothetical case where you've cut off the memory/IO strobes but CE is still being asserted by the active decoders it would assert whatever nothingness it sees on the card's end even though the actual devices are silent?
 
The configuration used by the LoTech card is pretty common - that is running the active low read strobe to the DIR pin on the bus buffer. When that is done, the high/in-active state of RDn drives A to B (implied write) which pushes the ISA side data to the card side. It's a common short cut to fully qualifying the buffer enable with activity strobes. No harm done to the ISA bus if phantom OEs happen.

In general (this example aside), it's not a good idea to do this. Combinatorial decode logic will often have different propagation times for different address lines - causing transient output states as all input levels stabilize and the end to end paths for each address line contribution quiesce.
 
The reason I worry it could actually be significant is when I was hacking around with my “ROM override” scheme I discovered, well, this (I explained it, sort of, in the linked thread):

All the peripherals on the Tandy 1000 motherboard itself are gated behind a ‘245; everything other than the CPU and its direct control circuitry are effectively positioned as if they were on a card plugged into the same bus segment as brought out to the connector. The ‘245 is controlled by a PAL, and the equation for CE is essentially:

enable if:

1. The ROM chip select is active or,
2. The line from the “big blue” chip that is an omnibus collection of all chip selects for all the other peripherals is active, unless a certain state is indicated by the DMA controller”.

That PAL has a tied-to-a-pull-up line on it that when pulled down disables the ROM chip select, which was the core of my override scheme. However, while that worked great for the segment of the 128k of ROM that resided at E0000 I discovered if I tried to put my own ROM contents at F0000 it would get trashed. The ROM CE disable worked, the built in DOS was gone, but the area above F000 where the ROM was disabled was full of pseudo-random garbage. (You will actually see the same garbage if you PEEK above F000 in an 1000 EX.) What I figured out was going on from reading the Big Blue datasheet was that case #2 of the PAL code was being activated, because that chip has built in decoding that activates that “online peripherals active” line for the entire F page. Thus the buffer comes on and pushes out trash that interfered with the ROM I had sitting on the expansion bus.

(I was able to successfully override this by abusing that DMA control line clause in the PAL; a solution that obviously wouldn’t work if I had the DMA controller, but since I don’t I have a perfectly functional XTIDE bios at F000 now.)

Anyway, that’s where my worry that just killing the I/O strobes wouldn’t be sufficient comes from. If a sloppily buffered card behaved like the Tandy motherboard trashing of overlapping IO or memory spaces could be a thing?

Whether it would actually be a thing with the VGA card I want to switch out... I would hope not? It’s a card new enough to basically be one big fat ASIC with some RAM chips and a BIOS ROM behind it, I would *hope* it fully qualifies everything with the strobes?
 
It would be at least semi reasonable for motherboard designers at the time to assume absolute dominion over the F UMA segment. It would never have been reasonable for expansion card designers to act that way
 
But in the same vein, it seems a perfectly reasonable assumption on the part of an expansion card designer to assume that if you’re plugged into a computer that’s turned on and the address bus indicates the peripherals on the card are selected it should be fine to grab the bus with your output buffer? It would be unexpected to see a bus cycle with a specific address but no read or write strobe ever happening?
 
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