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Improved RL01/RL02 disc simulator available

PDP11GY

PDP11GY

Experienced Member
Joined
Jun 20, 2009
Messages
145
Location
Munich/Germany
Hello,
the new Version V 3.04 is now available via my homepage with new features:
Speed improvement. DPR (Dual Ported Ram ) is now included in QSYS. Result: A memcpy is
replacing the previously used PIO based controlled I/O. Offline mode will now construct
Cylinder 0+1 and the bad sector file in memory.
Of course there are still further improvements possible, like supporting 2 RL drives
at the same time. I also plan to implement a PCB board with my friend Jonny Jonas ( www.timecontrol.de )
including also a small display and a faster way to access the SD-Card. Another open point here
is how to convert the TTL signals in to FPGA world. I used a resistor network and it works fine,
but it requires absolutely 100% grounding. Alternatively, we could use converter chips like HC4050
but that does not work for this implementation yet.
Reinhard
 
Hi All;
Reinhard, I Thank you for Your efforts, I have already Downloaded What I could of what I see You have available..
What I am Waiting for is a Board to Convert from RL Drives or any of the Big Washing Machine size drives to SeaGate ST506 MFM Drives.. There is a Hint on Your Web site that You have started to Do that, But, there is not much more than that there.. I do Not have any of the Big Disk Drives, But, I have the UniBus Interface Boards.. And Would love to use those to go to my ST506 Drives, IF possible..
THANK YOU Marty
 
Marty,
The ST506/ST412 MFM-Disc project is in progress but there are other problems.
It is rather not a technical problem, I lack the necessary information to continue
in this project. The lack of information is related to the low level disc format.
Each manufacturer has formated the discs different. E.g. A RQDX-1/2 formated disc
can't be used with a RQDX-3. and so on ... and so on....
Regards, Reinhard
 
Reinhard,

With respect, I think it might make more sense to finish the ST506 version of your drive emulator first. This should be simpler than the RL series was, there's no need for the line transceivers ICs used for the RL, is there?

As to the format problem - wouldn't it be possible to emulate the drive on a physical level, and use the original tools to format and initialize it? [I.E. - ZRQxx]

I realize it's not as sophisticated as your RL solution, but it would be universally compatible then.
 
Last edited:
Ok, the ST-506/412 is important for many people but I can not do everything alone.
My free time is limited and I am not a pensioner (Hope you understand my humor) :)
I understand very well the need of a ST-506/412 simulator. The timing is done but I
have no reference system to find out how the content of headers is implemented.
I'll give you an update.
 
Hi All;
Reinhard, I Thank You for Your response.. I admire what You have Done and what You have accomplished !!!
I think when I looked at Your site, there was NO information as far as the ST506 project, so Even If I wanted to build what you have and try and help You, there is not enough information there for the rest of Us to be of any help to You.. I am Sure that there are many people who would have the knowledge and or the expertise to help with this project..
So, Put out what You have and Maybe someone can help You overcome what ever problems that are present there or at least be able to give You some Ideas..
THANK YOU marty
 
PDP11GY said:
Ok, the ST-506/412 is important for many people but I can not do everything alone...
Click to expand...
What [hardware? software? documentation?] would I need to get for me to be of assistance to your effort?
 
I'll open a new thread with questions about ST506/ST412.It would be nice if you can help me.
At the moment I can not work continuously because my RD51 is broken. Unfortunately, I lack
the necessary information. I only have the Seagate Manuel for the ST506, = RD50. If I have
an up and running ST506/ST412 environment again, I will collect the data from one cylinder
to use it for reference purpose. Also, one major goal is to implement a "collect" mode. In
this case, the FPGA will control the disc and save the whole disc data content to SD-Card.
 
PDP11GY said:
Ok, the ST-506/412 is important for many people but I can not do everything alone.
My free time is limited and I am not a pensioner (Hope you understand my humor) :)
I understand very well the need of a ST-506/412 simulator. The timing is done but I
have no reference system to find out how the content of headers is implemented.
I'll give you an update.
Click to expand...

There are dozens of ST-412 controller implementations documented in disk controller manuals on bitsavers.
Try adaptec, cirrusLogic, codata, dec, dsd, dynabyte, emulex, konan. Western Digital and National have detailed
descriptions of their chip sets. National app note AN-0413_Disk_Interface_Design_Guide_and_Users_Manual_Jan86
is good. The biggest difference in sector formats is how they deal with error checking, and error correction.

cirrusLogic/Practical_Error-Correction_Design_For_Engineers_2ed_1991 has a good discussion on that.

you will also run into compensating for write-precompensation in the controller if you work at the bit level on sectors.
 
Last edited:
Al Kossow said:
If you are using an RQDX3, the controller uses an SMC 9224. The sector format is described on page
617 of http://bitsavers.org/pdf/standardMicrosystems/_dataBooks/1988_StandardMicrosystems.pdf

The CRC and ECC polynomials are on page 610
Click to expand...

The classiccmp thread
http://marc.info/?l=classiccmp&m=129644470316554&w=2

is also worth looking at for more info on ECC, and some errata on the National app note.

Philip is the person who developed the diskferret. It's unfortunate that the hard disk reading firmware for it appears to be stalled.
 
Hello,
I want to refere to my thread "RL02-RL01-simulator-project-is-finished" with the answer/analysis from Lou, January 14th, 2014.
Status: The problem occurred only if the reset button on the PDP11 was pressed to force the write to the SD-card. The problem
The problem does not happen if the reset butten on the DE0-Nano will be pressed to force the write to the SD-Card. The NIOS II
software is monitoring the power-OK line and the DE0-Nano reset button. For me it seems to be, that the PDP11 reset also has an
influence to the write gate signal ? On a real RL02, a reset would force an immediate head home positioning but this feature
can't be implemented in my simulator. At this point in time, I would say it is a feature, not a bug and I recommend to use the
DE0-Nano reset button instead of the PDP11 reset button. As soon as it is possible, I will analyze the problem continues or
one of you ? My guess is, that the TTL-Power-ok signal can properly monitored concerning trigger level. My question is at which
power level is the power ok signal no longer valid ? Also here, it is a logic level converter issue.
 
The problem must have been my poor workmanship ...

The problem must have been my poor workmanship ...

Reinhard,

For the past two weeks, I have been working on getting your RL02 emulator running well on my pdp-8/a and RL8A. Tonight I am finally successful, however only after cleaning up some of my previous mess. I have also found that after this cleanup, the pack image in ram saves to SD card with no problem - no need to reposition the heads over track zero. I think I may have been too sloppy with the handling of the signals from the 75107s.

So tonight I have a bootable RL02 OS/8 pack image that boots clean every time, can be read and written to fine, and passes the AJRLLA pack checker diagnostic every time with no errors! The pdp-8/a is quite fast when it has a fast disk to work with.

Although in the previous "messy" state I had the emulator working on the RLV12, it did not work well at all on the RL8A. When the 16-bit drive command would be sent from the RL8A, it would often have bits corrupted when received at the emulator (as displayed on the debug console.) I played with the system clock level shifting voltage divider and filter capacitor a little bit, thinking I could make it a little better, but it would not consistently work perfectly. I decided that I was tired of dealing with the voltage dividers, and so I tore them all out and replaced all but the power OK divider with one 74LVC245. It works really nice!!!! If you and Jonny make a printed circuit board, I suggest this instead of the voltage divider resistors.

However, I still had occasional errors on the received drive command word. I looked at the command line and system clock timing with the logic analyzer. I think the command data set-up time should have been long enough before the system clock low-to-high transition latched in each bit, but I could see from the way the error manifested on the debug console that perhaps a little longer would help. I used a 20ns delay line I had around to delay the system clock by that amount. (I wanted to try various delays, but I had no 7431s around). That little additional setup time did the trick! Now the command is always read perfectly.

I now need to go back to the RLV12 and make sure everything works there, including proper saving of the ram back to SD.

Here are some pictures of the work:


http://www.vintage-computer.com/vcforum/album.php?albumid=184&attachmentid=17223
http://www.vintage-computer.com/vcforum/album.php?albumid=184&attachmentid=17224
http://www.vintage-computer.com/vcforum/album.php?albumid=184&attachmentid=17225

Thanks for your help and patience,
Lou
 
Lou,
Your message makes me very happy. Particularly interesting is the news that my Simulator now also runs in a RL8A
controller based environment. Thank you for the good cooperation. Would be nice if you can make an OS/8, SD-Card
based image available ( via E-Mail?).
I just have a problem understanding your issue concerning command data and a 20ns delay. Generally, a delay
is very easy to implement with verilog using the system clock and D-FF's, running at 65.6 Mz. The question is, why do
we need the delay. In my case/my implementation it is not necessary. If I look in the schematics of the RL drive, there
are a lot of TTL-Gates involved which make in total a delay which is not mapped in the FPGA environment which is
designed fully syncron.
Regards, Reinhard
 
Hi All;
Reinhard, in Your Implementation of the RL Drive, are you using an RL Drive interface that then goes to Your FPGA ??
The Reason I ask is I have an RL Controller Card (M7762), but No Drive to attach it to..
Can This Card be used with Your Implementation ??
I also have an M7982 UniBus to Serial Bus Controller Card, I don't know what this Card is for, or If it would be of any Help..
THANK YOU Marty
 
Marty,
a RL drive is not necessary , only a 40 pin flat-cable going from the controller to the simulator.
**** But ****
Do not forget to terminate the RL-bus at the simulator side via resistors like it is implemented on a
real RL-drive.
Regards, Reinhard
 
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