glitch
Veteran Member
I got the aforementioned SC Digital SRAM board jumpered properly after tracing the tracks to the DIP switches, and discovered it's a 100% functional board, and fast enough to use with my Cromemco ZPU with no wait states. Since having a stable RAM board means I can use my 4FDC and it's ROM monitor, I decided to redo an 8K RAM board I started wire-wrapping when I began restoring the Z-2D.
After drawing the circuit out on paper, I figured out that all I needed to drive 8K static devices was a 74LS138 1-of-8 decoder and a 74LS00 quad NAND gate, a few 74LS245 bus transceivers to transition from two unidirectional 8-bit buses and the RAM/ROM bidirectional bus, and the devices themselves. Multiple enable/select inputs on the memories and the 74LS138 allowed me to integrate phantom support, MEMWR generation, and I/O blocking with no additional ICs than those mentioned. Since the 6264 SRAM and 2764 EPROM share highly similar pinouts, I'm able to use either in the sockets with no jumpers (of course, you can't currently write to the EPROMs with this board...but adding the capability should be trivial). Pictures of the wire-wrapped prototype and testing it with my development system (S-100 backplane with ZPU, 4FDC, 16K SRAM and proto board, with the Kaypro II as a 1200 baud console) attached.
Anyway, I was wondering if anyone is interested in this project, at least interested enough for me to turn the prototype into a PCB. The parts count should be very low. I'd probably add address buffering into a design with multiple SRAMs, as well as battery or supercap backup options. It could be offered in kit form, or pre-assembled and tested for those needing a verified working RAM board to get other S-100 systems up and running.
After drawing the circuit out on paper, I figured out that all I needed to drive 8K static devices was a 74LS138 1-of-8 decoder and a 74LS00 quad NAND gate, a few 74LS245 bus transceivers to transition from two unidirectional 8-bit buses and the RAM/ROM bidirectional bus, and the devices themselves. Multiple enable/select inputs on the memories and the 74LS138 allowed me to integrate phantom support, MEMWR generation, and I/O blocking with no additional ICs than those mentioned. Since the 6264 SRAM and 2764 EPROM share highly similar pinouts, I'm able to use either in the sockets with no jumpers (of course, you can't currently write to the EPROMs with this board...but adding the capability should be trivial). Pictures of the wire-wrapped prototype and testing it with my development system (S-100 backplane with ZPU, 4FDC, 16K SRAM and proto board, with the Kaypro II as a 1200 baud console) attached.
Anyway, I was wondering if anyone is interested in this project, at least interested enough for me to turn the prototype into a PCB. The parts count should be very low. I'd probably add address buffering into a design with multiple SRAMs, as well as battery or supercap backup options. It could be offered in kit form, or pre-assembled and tested for those needing a verified working RAM board to get other S-100 systems up and running.