Ok, I was looking at the code it may be able to run at FC00. This would be with either a dead U4 or a failure of the debug board to bring U4-12 to zero. I have to dig up the schematics and look to see how the release circuit works but I recall it used a 74LS74. The reset pin would cause it to go to one state and a read of the address would cause it to change state, bringing U4-12 to 0.
The code is dual mapped. Still the Error light routine is executed with a jump to 0D00h. I don't know how it could get there if the code continued to run at FC00h. It should reach the point that is would reach the error condition and then attempt to jump to 0D00h from some place between 0C00h and 0D00h. if it were trying to continue to run at FC00h the processor's addresses would go to 0D00h and then just execute until it reached FC00h again where it would just loop back to 0D00h without executing the error routine.
At least that is my thinking.
Now that I've convinced myself that the debug board could not run the error routine without U4 decoding K3 ( 0C00-0FFF ), lets look at what else might be the problem.
I'm looking at the schematic:
http://www.classiccmp.org/cini/pdf/Rockwell/Rockwell KIM-1.pdf
It shows that U15 and U16 are needed for the RAM to be working. Some of the stages of U16 are need to create the two phases of clock 2. The debug board also needs these two clocks. U15 is not needed for the debug board.
So, without using a scope or logic probe, I would put the possible likely failure points, in desending order as:
U15
U16
U4
one of U13 or U14 enable pins stuck high
one of the RAMs holding the R/W or CS*
The 6502 addressing ( not to likely as it seems to be working )
A logic probe or scope could look at these to see what was more likely. Remember that when you reach a failing point it is not easy to determine if it is a failing output or a failing input that is holding a line in a particular state. Usually it is the driving side but it still could be a stuck input.
Dwight