shirsch
Veteran Member
After the first one turned out to be a dud, I picked up a second M8192-YB w/ FP chip and installed it in my modified (22-bit) Heath H-11 backplane along with a QBone to emulate memory, storage, console and ltc interrupt. First order of business was to run the ZKDJB2.BIC CPU test for 11/73. It fails the BEVENT register checks starting at test code 01166. If I suppress the BEVENT test by setting the appropriate bit in the configuration register it passes everything else. All other tests (memory, cache, memory mapping, etc) pass 100%. The ZKDJ test requires that that halt-on-trap be disabled by inserting jumper W9 on the CPU board. Problem is that the M8192 documentation calls out W5 for this function and lists W9 as a disable for the BEVENT reqister. I've tried all combinations of W5 and W9 with no change in the (failing) result. Before I assume the CPU has a hardware defect, I wanted to double check that I'm not doing something dumb to cause the problem. I have verified that the BEVENT signal appears on the bus and tried (individually) both the 50 Hz. signal generated by the QBone and the 60 Hz. signal available from the Heath power supply.
Advice?
Advice?