I'm sure at least some of you guys know this, but in this online pro manual:
Guide to Writing a P /OS 1/0 Driver and Advanced Programmer's Notes
Chapter 9 has info on accessing video registers and video memory:
9.1.4 Access to Video Memory Through the Bus It is possible for the CPU to read from and write to the video display memory without using the device registers - because the memory can be programmed to be on the bus. P/OS uses this configuration. The video memory occupies a partition called BITMAP, and the system video handler creates a region called TFWBMP, which fills it. An application can attach the region and map to all or a portion of it.
TFWBMP is 32KB, of which the first 30KB corresponds to the displayed portion of the memory. Note that the least significant portion of the first word of the region corresponds to the upper left corner of the screen. .If there is an Extended Bit Option (EBO) in the system, all three planes of memory share the same 32KB bus address space. To read from or write to any of the planes (whether or not there is an EBO), the memory reference enable bit (bit 5) in its plane control register must be set to 1. If there is an EBO, the memory reference enable bit can be set for more than one plane. Reads will come from each plane - in ascending order (1, 2, 3) that has the memory reference enable bit set. Plane numbers are defined by the hardware and do not nBcessarily correspond to any software numbering scheme. Writes will go to all planes that have the memory reference enable bit set. Remember that a transfer, once started, can take a long time. Check the Done bit before modifying any registers other than the X and Y registers unless you are certain that the transfer is complete.
Guide to Writing a P /OS 1/0 Driver and Advanced Programmer's Notes
Chapter 9 has info on accessing video registers and video memory:
9.1.4 Access to Video Memory Through the Bus It is possible for the CPU to read from and write to the video display memory without using the device registers - because the memory can be programmed to be on the bus. P/OS uses this configuration. The video memory occupies a partition called BITMAP, and the system video handler creates a region called TFWBMP, which fills it. An application can attach the region and map to all or a portion of it.
TFWBMP is 32KB, of which the first 30KB corresponds to the displayed portion of the memory. Note that the least significant portion of the first word of the region corresponds to the upper left corner of the screen. .If there is an Extended Bit Option (EBO) in the system, all three planes of memory share the same 32KB bus address space. To read from or write to any of the planes (whether or not there is an EBO), the memory reference enable bit (bit 5) in its plane control register must be set to 1. If there is an EBO, the memory reference enable bit can be set for more than one plane. Reads will come from each plane - in ascending order (1, 2, 3) that has the memory reference enable bit set. Plane numbers are defined by the hardware and do not nBcessarily correspond to any software numbering scheme. Writes will go to all planes that have the memory reference enable bit set. Remember that a transfer, once started, can take a long time. Check the Done bit before modifying any registers other than the X and Y registers unless you are certain that the transfer is complete.