Ok, if you look at the schematics for the front panel you should notice that all of the 7405 gates (including the address/data switches) are divided into four (4) groups driven by the signals LAD, HAD, C3 and NOOP.
The four groups are connected to a common bus going to socket U2.
A 7405 gate is an open collector inverter. As such, they do not have a pull-up to 5V. The pulls-up resistors are all on the CPU board (after U2).
First thing, after a power-up, STOP and RESET; can you measure the state of signals LAD, HAD, C3 and NOOP using your logic probe.
They should all be LOW with no pulses on them.
A LOW input to the 7405 gates should make the outputs all float. If all of the address/data switches are CLOSED, your logic probe should read all HIGH signals on socket U2.
That is the first test.
Let me know what you obtain.
Dave