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PDP-12 #435 at the University of Minnesota Duluth

I'm on the road, so I'm following the discussion, but not able to spend any time looking things up or figuring stuff out for you. I'll be more use next week. Meanwhile, today is to be a long driving day, and I haven't looked at what my wife's got us doing yet for the rest of the week.

Vince
 
I don't have any advice on which diagnostics to run, but my understanding is that the TC12 has a rather comprehensive maintenance mode.

The TC12 can flip bits in a maintenance register to simulate data that normally comes from a LINCtape drive. The only parts that it can't test are the LINCtape drives, the cables, and G888 FlipChips.
 
The TC12 maintenance register can asynchronously set and clear the TAPE WORD flip-flop. The maintenance register can also simulate TP3 and TP0 pulses, which clock the LC01 and LC00 flip-flops, which synchronously set the TAPE WORD flip-flop. The status of LC01 and LC00 can be read in maintenance mode. I don't see a way for it to directly read the status of TAPE WORD, so SXL is probably the only way.

Regardless, I would say it is highly likely that the TC12 diagnostics can test that flip-flop without a working transport.
 
I tried running some code where I clear the FF using IOT 6152, generate TT0 & TT3 using IOT 6151, then use TWC/SXL 17 to determine if the FF got set.
Running that code in a loop, it seems that FF is getting set (TWC is skipping)... sometimes? The amount of tries it takes for it to set is inconsistent, sometimes it'll set almost immediately, sometimes it'll take ~a second.
EDIT: Also if I run the same code but don't generate TT0 and/or TT3 it'll never skip, as expected.

This is the code I'm running, definitely yell at me if I'm doing something stupid :p
Code:
4020    1020    LDA I       // Set AC bit 4 so IOT 6152 clear tape word FF
4021    0200
4022    0500    IOB
4023    6152    IOT 6152
4024    0437    TWC I       // Really make sure tape word FF is clear
4025    6024    JMP 4024
4026    1020    LDA I       // Set AC bits 6 & 7 so IOT 6151 generates TT0 & TT3
4027    0060
4030    0500    IOB
4031    6151    IOT 6151
4032    0417    TWC         // Check if tape word FF is set
4033    6020    JMP 4020
4034    0000    HLT
 
Last edited:
Can you try swapping the M113 in C16 with another? That would help determine if it's an LC02 (which generates LC01 and LC00) issue.
 
I once had a problem that I think was a broken wire wrap wire. It acted like there was an RC network in the path. The first pulse would go through, but subsequent pulses in a pulse train would not get seen. I added a wire in parallel, and it has worked fine since.

So, if the M113 output looks right, but the M216 input doesn't...

Vince
 
Can you try swapping the M113 in C16 with another? That would help determine if it's an LC02 (which generates LC01 and LC00) issue.
I swapped M113 in D24 (KW12) with M113 in C16 (TC12). Running @ZachyCatGames program gives the same result, which is that it takes a random amount of time to halt.

So, if the M113 output looks right, but the M216 input doesn't...
Thanks. It may be time to scope these pins.
 
Yep! We will eagerly await 'scope captures!
Quick question... is there anything dangerous about using a typical multi-meter's tone feature to check for continuity between pins of the backplane? I know that the audible signal isn't enough to confirm a robust enough electrical connection for logic, but could I safely use it to confirm that two pins were connected by wire wrap?
 
Quick question... is there anything dangerous about using a typical multi-meter's tone feature to check for continuity between pins of the backplane? I know that the audible signal isn't enough to confirm a robust enough electrical connection for logic, but could I safely use it to confirm that two pins were connected by wire wrap?
For the most part, yes. While it is possible to get a false positive it is extremely unlikely. And quite low probability of damaging something if you are on the wrong pins.
 
We went and scoped a few things while running my above program:
Code:
4020    1020    LDA I       // Set AC bit 4 so IOT 6152 clear tape word FF
4021    0200
4022    0500    IOB
4023    6152    IOT 6152
4024    0437    TWC I       // Really make sure tape word FF is clear
4025    6024    JMP 4024
4026    1020    LDA I       // Set AC bits 6 & 7 so IOT 6151 generates TT0 & TT3
4027    0060
4030    0500    IOB
4031    6151    IOT 6151
4032    0417    TWC         // Check if tape word FF is set
4033    6020    JMP 4020
4034    0000    HLT

We checked both ends of the connection between LTS LC 02 (0)H and the LTS LC 01 flipflop (C16 S2 and D19 N1):

Screenshot_20240912_105144.png
Which we think looks fine?

Then we checked both ends of the connection between the LTS LC 00 FF and the Tape Word FF (D19 V2 and D19 C1) and the connection between the LTS LC 01 FF and the Tape Word FF (D19 S1 and D19 B1):
Yellow: D19 V2
Red: D19 C1
Blue: D19 S1
Green: D19 B1
View attachment Screencast_20240912_114245.webm
Which we think looks like a bunch of garbage/nonsense, though we did find it odd that the matching pairs didn't usually have the same voltage.
We also tried checking both ends of both connections w/ a multi-meter and got nothing, but we aren't sure if that's because we're getting no connection at all or if we're getting a super dodgy connection.

Later today we're planning to check the connections from the LTS LC 00 & 01 FFs into themselves (D19 U1, P1, V1, and T2) to see if there's anything funky going on there.
 
It would be most helpful to provide a single capture triggered on the edge one of the signals rather than a video of the oscilloscope free running. You may need to adjust your timebase to fit a reasonable number of pulses on the screen.

If you mimic the timing diagrams in Volume III, that would also be quite good (though I suspect there may be an error in the timing diagram relative to the setting of the second and following TAPE WORD pulses).
 
We have a Saleae logic analyzer that we bought when Julian was around, but never ended up using on the PDP. I was thinking about hooking that up tomorrow since it would give us a view of more pins at once. Any gotchas to worry about with using a logic analyzer on the low-voltage logic of a PDP?

I assume the procedure is to hook up to the pins and then also attach to ground... Any other advice?
 
Any gotchas to worry about with using a logic analyzer on the low-voltage logic of a PDP?
Heh. 5V TTL is considered high voltage by today's standards! But no, you shouldn't have any issues. And yes, just ensure you have a ground connected.
 
Heh. 5V TTL is considered high voltage by today's standards! But no, you shouldn't have any issues. And yes, just ensure you have a ground connected.
Great thanks!

I meant to say, Zach and I scoped a bit more today but things were so weird I don't even know how to describe it. We will try again tomorrow, probably with the Saleae.

Is the best practice to use a ground pin on one of the cards being tested (e.g. C2), some other common ground, or (as @ZachyCatGames has asked), can we just attach to the chassis?
 
I like to use a close and convenient ground like C2, but as long as you've confirmed a spot on the chassis is indeed connected to ground (not always the case), that should be fine as well. It's good practice to keep the ground lead relatively short, but not required.
 
So, @ZachyCatGames hooked up our Saleae Logic Pro 16 and scoped some of the signals around LC00 and LC01 while running Zach's code. The things we were looking at are on Page 145 of the MM Vol. III:
1726254844738.png

What we saw didn't make a lot of sense -- signals at S2 and N1 were extremely rare (which is different than our oscilloscope screenshot from the other day).

So, we decided to scope just four things: LTT TP0 L (M113 C16 P1), LTT TP3 L (M113 C16 R2), LTS LC 02 1 (H) (M113 C16 S1), and LTS LC 02 (0) H (M113 C16 S2) -- the NOR clock in C16.

When we did that, TP0 (P1), TP3 (R2), and 02 (1) H (S1) all seemed "normal" (or at least consistent), but 02 (0) H (S2, which feeds D19 N1), was very inconsistent. Since all the signals are on the same card (no wire wrap involved), I swapped the M113 back from before (recall that I swapped two the other day), and i also tried to clean the clip chip slot with some deoxit and paper towel on the flip chip for C16. When we next captured, the signal on S2 seemed improved, but is still quite flaky:
1726260703858.png


If you zoom in, it looks even weirder:
1726260775402.png

P1, R2, and S1 all have signals of roughly the same length (~60ns), but the S2 changes -- when they happen to occur -- are tiny, in the single digit ns. I don't know if those are instrumentation glitches, or what. Zach added a speaker click to when the Tape Word Flip Flop is set, and we can hear that it is getting set, but very inconsistently.

So, what would you suggest as a next step? Should I try to give the FC slot a deep clean? How should I go about doing that? Am I misunderstanding what I'm seeing here, or what the LC 02 (0) H signal should look like? I'll attach the capture file, which can be viewed in Saleae's Logic 2 program.

Any advice will be greatly appreciated!
 

Attachments

  • C16_timer_signal-post-cleaning.zip
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I think you should go back to the oscilloscope to understand what the signals really look like.

What is the sample rate you're using for the Saleae?
 
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