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Cbm 2001 Pet strange boot

Thanks at all!

Nivag Swerdna said:
To the OP, having multiple faults in succession isn't at all unusual, these things are old and if they haven't failed already they contain plenty of parts that are on the verge of failing. Repair is a constant process not a one off with these beauties.

Let's have some measurements and go for the 2nd pass....

F2 and F4?
Click to expand...
Ok Nivag, when i come back from my job i'll try to remeasure F2 and i'll measure F4!
 
So:

F2

pin1: pulse
pin2: pulse
pin3: pulse
pin4: pulse
pin5: pulse
pin6: pulse
pin7: low
pin8: pulse
pin9: pulse
pin10: pulse
pin11: pulse
pin12: pulse
pin13: high
pin14: high
 
F4

pin1: pulse
pin2: pulse
pin3: pulse
pin4: pulse
pin5: pulse
pin6: pulse
pin7: low
pin8: pulse
pin9: pulse
pin10: low
pin11: pulse
pin12: pulse
pin13: high
pin14: high
 
H8

pin1: low
pin2: low
pin3: high
pin4: high
pin5: high
pin6: low
pin7: low
pin8: high
pin9: low
pin10: high
pin11: low
pin12: low
pin13: high
pin14: high
 
G8

pin1: no signal
pin2: no signal
pin3: no signal
pin4: no signal
pin5: low
pin6: high
pin7: low
pin8: high
pin9: low
pin10: high
pin11: pulse
pin12: low
pin13: pulse
pin14: high
 
Well G8 p12 should not be stuck low.... My next random device would be....

All pins of G2... Please...

(Taking a binary chop approach weighted by things that often fail)
 
G2

pin1: pulse
pin2: low
pin3: no signal
pin4: pulse
pin5: high
pin6: high
pin7: low
pin8: pulse
pin9: pulse
pin10: pulse
pin11: no signal
pin12: pulse
pin13: pulse
pin14: high
 
Dave_C78 said:
Hi Hugo i have 10,4 V across this capacitor!
Click to expand...
Is that with the meter or the scope ? The main thing is to check on the scope, the ripple voltage, that the voltage is not falling down between charging peaks enough to put dips in the voltage regulator's output.

( A had a go on my PET to confuse the 4 state circuit by force resetting one of the flip flops to see if it could be knocked out of step in its counting sequence with respect to the clock pulses, but it does seem to naturally right itself, so the theory that it was being upset by glitches in the power supply probably does not have any merit )
 
Hugo Holden said:
Is that with the meter or the scope ? The main thing is to check on the scope, the ripple voltage, that the voltage is not falling down between charging peaks enough to put dips in the voltage regulator's output.

( A had a go on my PET to confuse the 4 state circuit by force resetting one of the flip flops to see if it could be knocked out of step in its counting sequence with respect to the clock pulses, but it does seem to naturally right itself, so the theory that it was being upset by glitches in the power supply probably does not have any merit )
Click to expand...
Digital multimeter!
 
H5

pin1: high
pin2: low
pin3: high
pin4: low
pin5: pulse
pin6: high
pin7: low
pin8: low
pin9: high
pin10: high
pin11: pulse
pin12: high
pin13: pulse
pin14: high
 
So looking at the schematic.. H5p8 being LO means G1p3 will always be LO... which is incorrect.

G2 p9,10,12&13 pulsing and G2p8 pulsing suggest F2, G2 and G3 OK

H5 p4 LO is incorrect

Now H5 p4 comes from F4 p10 which is LO... which doesn't seem right

F4 p10 is fed from G3 p19 and is the latched version of F4 p9 which is pulsing.

From the above we suspect G3 is OK... so that suggests perhaps a poor contacts and trace between G3 p19 and F4 p10

What's happening at G3? Maybe de-oxit and wiggle G3 and F4? Check pins of G3 and F4 are happily in their sockets... especially if you fiddled with F4 earlier. ;)

Please post the signals at G3.... p18 and p19 are of particular interest!
 
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Not to distract from the fault finding sequence (good job Nivag), the /INIT line still has me intrigued. In other cases in the computer's circuitry, where a pullup resistor is used, it is not given a named signal.

An /INIT label describes a definite signal name (?initialize) that is active low and given a test point number. This signal when low would also establish the reset & operating conditions of a number of the IC's including the 4 state machine. Yet, there is no IC output connection (seen on the schematic) that drives it low at any specific time and it may only be low very transiently at power up. If I force it low transiently after power up, the computer locks up. Also I'm not sure how the 4 state machine was able to correct itself I deliberately corrupted its logic (counting) sequence. Suggesting it might have somehow received a brief reset pulse from /INIT to reset the two flip flops. As noted in the timing diagram, the two flip flops Q outputs need to be high, before the first pulse of the group of 4 clock pulses around the vertical blanking time occur. If there is a reset pulse on /INIT, it would have to occur, coincident with the second pulse or just prior to the 3rd pulse in the group of 4 pulses to ensure both the Q outputs were low.

Many years ago while working on a very large TTL based game that had a very peculiar fault, there was a single pullup resistor used to tie up the unused inputs on about 30 of the IC's. One IC had failed and was somehow able to inject a pulse on one of its input pins and that pulse affected all the other IC's on that line. I'll do some more study on the /INIT line and see what I can learn.
 
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On the subject of nINIT... I've seen the case where this signal is a pull-up but where an EPROM has been fitted... the EPROM having a VPP pin rather than a CS of an original mask ROM... in this case the EPROM has enough oompf to pull down the pull-up and mayhem ensues. I'm not completely clear on the history of pulling up... a more modern approach is just to connect to the positive rail rather than fighting each other for the pull-up.
 
Nivag Swerdna said:
On the subject of nINIT... I've seen the case where this signal is a pull-up but where an EPROM has been fitted... the EPROM having a VPP pin rather than a CS of an original mask ROM... in this case the EPROM has enough oompf to pull down the pull-up and mayhem ensues. I'm not completely clear on the history of pulling up... a more modern approach is just to connect to the positive rail rather than fighting each other for the pull-up.
Click to expand...
Interesting.

On the history of pullups, even without the pullup resistor, the TTL floating input self pulls up to around 3V area, or logic high. Some TTL designs I have seen just leave the open inputs floating for this reason, but it is not thought to be good practice. It was recommended for noise immunity that is is better to pull it up to the 5V rail. So many boards simply have the one 1k pull up resistor shared by multiple unused IC inputs required to be logic high.

Another reason to use a pullup is on the output of a TTL IC, say of you want to interface that with a cmos IC because of the input threshold of the cmos IC not suiting the TTL output directly.
 
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